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[70.53.205.21]) by smtp.gmail.com with ESMTPSA id q188-20020a37a7c5000000b0069fc13ce208sm3187880qke.57.2022.05.06.15.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 15:57:12 -0700 (PDT) From: Yannick Brosseau To: jic23@kernel.org, lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, fabrice.gasnier@foss.st.com, olivier.moysan@foss.st.com Cc: paul@crapouillou.net, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yannick Brosseau Subject: [PATCH 2/2] iio: adc: stm32: Fix check for spurious IRQs on STM32F4 Date: Fri, 6 May 2022 18:56:17 -0400 Message-Id: <20220506225617.1774604-3-yannick.brosseau@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220506225617.1774604-1-yannick.brosseau@gmail.com> References: <20220506225617.1774604-1-yannick.brosseau@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The check for spurious IRQs introduced in 695e2f5c289bb assumed that the bits in the control and status registers are aligned. This is true for the H7 and MP1 version, but not the F4. Instead of comparing both registers bitwise, we check the bit in the status and control for each interrupt we are interested in. Signed-off-by: Yannick Brosseau --- drivers/iio/adc/stm32-adc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index a68ecbda6480..5b0f138333ee 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -1422,9 +1422,10 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) return IRQ_HANDLED; } - if (!(status & mask)) + if(!((status & regs->isr_eoc.mask) && (mask & regs->ier_eoc.mask)) || + ((status & regs->isr_ovr.mask) && (mask & regs->ier_ovr.mask))) dev_err_ratelimited(&indio_dev->dev, - "Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n", + "Unexpected IRQ: CR1/IER=0x%08x, SR/ISR=0x%08x\n", mask, status); return IRQ_NONE; @@ -1438,7 +1439,9 @@ static irqreturn_t stm32_adc_isr(int irq, void *data) u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg); - if (!(status & mask)) + /* Check that we have the interrupt we care about are enabled and active */ + if(!((status & regs->isr_eoc.mask) && (mask & regs->ier_eoc.mask)) || + ((status & regs->isr_ovr.mask) && (mask & regs->ier_ovr.mask))) return IRQ_WAKE_THREAD; if (status & regs->isr_ovr.mask) {