From patchwork Sun May 8 17:56:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 12842556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B51AC433F5 for ; Sun, 8 May 2022 19:11:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231435AbiEHTPk (ORCPT ); Sun, 8 May 2022 15:15:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236431AbiEHR4n (ORCPT ); Sun, 8 May 2022 13:56:43 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A572EDFEA for ; Sun, 8 May 2022 10:52:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5FAAFB80E3F for ; Sun, 8 May 2022 17:52:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99467C385AF; Sun, 8 May 2022 17:52:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652032370; bh=T5pwX6o44Wr8PyyefbNocyJqyKPsQ4Y7W4rONivg8x0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aJ4AQUpSDPFl1p52Cbs5gxxHoNvJjGToE4JR9qHakol363o3jpM2jeyHjbUSktK7+ 90VPW1FIh2uRP6Lt920sMVVdPLB+MG5IE+QWOiLU3yT1OdObkZYGm6p5uXpCcLd7rX jDmAPnO08mfTSTRwjp5ENEJ1T4glzixSDnfsFBuyeScfZp9KOViJsWjPpAjY8WJQMw vc0kiOJa4Dy7QkA/3lBZDrZXnqL0ZcanJIJCwEjfb8Ua6a5DvACXzSV5VDYcD103s6 3Es1OClmPZTD78ahbBljvbREyjJPsZKfLL30gk/E9NO69FlQ9pno07lOZX9gBZRtwG 43gO+hcBtO7EA== From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Alexandru Lazar , Akinobu Mita , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?utf-8?q?M=C3=A5rten_Lindahl?= , Matt Ranostay , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , =?utf-8?q?Nuno_S=C3=A1?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Cameron Subject: [PATCH v2 30/92] iio: adc: ti-adc108s102: Fix alignment for DMA safety Date: Sun, 8 May 2022 18:56:10 +0100 Message-Id: <20220508175712.647246-31-jic23@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508175712.647246-1-jic23@kernel.org> References: <20220508175712.647246-1-jic23@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Jonathan Cameron ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Dual fixes tags as two cases that were introduced in different patches. One of those patches is a fix however and likely to have been backported to stable kernels. Note the second alignment marking is likely to be unnecessary, but is left for now to keep this fix simple. Fixes: 3691e5a69449 ("iio: adc: add driver for the ti-adc084s021 chip") Fixes: cbe5c6977604 ("iio: adc: ti-adc108s102: Fix alignment of buffer pushed to iio buffers.") Signed-off-by: Jonathan Cameron Acked-by: Nuno Sá --- drivers/iio/adc/ti-adc108s102.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c index c8e48881c37f..c82a161630e1 100644 --- a/drivers/iio/adc/ti-adc108s102.c +++ b/drivers/iio/adc/ti-adc108s102.c @@ -77,8 +77,8 @@ struct adc108s102_state { * tx_buf: 8 channel read commands, plus 1 dummy command * rx_buf: 1 dummy response, 8 channel responses */ - __be16 rx_buf[9] ____cacheline_aligned; - __be16 tx_buf[9] ____cacheline_aligned; + __be16 rx_buf[9] __aligned(IIO_DMA_MINALIGN); + __be16 tx_buf[9] __aligned(IIO_DMA_MINALIGN); }; #define ADC108S102_V_CHAN(index) \