From patchwork Sun May 8 17:55:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 12842618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13BA9C433F5 for ; Sun, 8 May 2022 19:14:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229736AbiEHTSg (ORCPT ); Sun, 8 May 2022 15:18:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239036AbiEHRxd (ORCPT ); Sun, 8 May 2022 13:53:33 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74C75DFC5 for ; Sun, 8 May 2022 10:49:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0DFDD61286 for ; Sun, 8 May 2022 17:49:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39144C385B0; Sun, 8 May 2022 17:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652032182; bh=hjQgsBhbT7ICmgPO0M6ZbutIAZpaN/baR8k265nazXA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FfJWBXwjm0zWltzpWyAm750dLvdjXPX0kr7EyCz1m/szF2dvEowkckngH2Z2m3Y3F U0lnwdw3W1suN9wTciQYf5s1cNx9e6CYkhQtyoyISj21R/Y8l3mhwytigoUTKDBfJP 06QVN92XFUHkUZKR1L25XHz5jdycC/NHC6V4za348ySh0Ug2vtLrNvRgwTC1+wXF8u KF+X3iF5jOcEVFNWAcx1qOLaJShFyfAxlG8FycO62nz8nxYLtqyELD0ORKNue+yzpT 7Uk2XGfnHSMv91NTU6142c8E+QXvVTCo8Hr+yThmb705Waftl9scREhB8t+yqpdPkp SH9ISEidMmfQQ== From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Alexandru Lazar , Akinobu Mita , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?utf-8?q?M=C3=A5rten_Lindahl?= , Matt Ranostay , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , =?utf-8?q?Nuno_S=C3=A1?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Cameron , Cosmin Tanislav Subject: [PATCH v2 04/92] iio: accel: adxl367: Fix alignment for DMA safety Date: Sun, 8 May 2022 18:55:44 +0100 Message-Id: <20220508175712.647246-5-jic23@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508175712.647246-1-jic23@kernel.org> References: <20220508175712.647246-1-jic23@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Jonathan Cameron ____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Update comment to reflect that DMA safety may require separate cachelines. Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver") Signed-off-by: Jonathan Cameron Cc: Cosmin Tanislav Acked-by: Nuno Sá --- drivers/iio/accel/adxl367.c | 2 +- drivers/iio/accel/adxl367_spi.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c index 62960134ea19..d680bec05efc 100644 --- a/drivers/iio/accel/adxl367.c +++ b/drivers/iio/accel/adxl367.c @@ -179,7 +179,7 @@ struct adxl367_state { unsigned int fifo_set_size; unsigned int fifo_watermark; - __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned; + __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); __be16 sample_buf; u8 act_threshold_buf[2]; u8 inact_time_buf[2]; diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c index 26dfc821ebbe..118c894015a5 100644 --- a/drivers/iio/accel/adxl367_spi.c +++ b/drivers/iio/accel/adxl367_spi.c @@ -9,6 +9,8 @@ #include #include +#include + #include "adxl367.h" #define ADXL367_SPI_WRITE_COMMAND 0x0A @@ -28,10 +30,10 @@ struct adxl367_spi_state { struct spi_transfer fifo_xfer[2]; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - u8 reg_write_tx_buf[1] ____cacheline_aligned; + u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN); u8 reg_read_tx_buf[2]; u8 fifo_tx_buf[1]; };