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[v2,91/92] iio: temp: max31865: Fix alignment for DMA safety

Message ID 20220508175712.647246-92-jic23@kernel.org (mailing list archive)
State Accepted
Headers show
Series IIO: Fix alignment of buffers for DMA | expand

Commit Message

Jonathan Cameron May 8, 2022, 5:57 p.m. UTC 
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition

Fixes: e112dc4e18ea ("iio: temperature: Add MAX31865 RTD Support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Navin Sankar Velliangiri <navin@linumiz.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
---
 drivers/iio/temperature/max31865.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/drivers/iio/temperature/max31865.c b/drivers/iio/temperature/max31865.c
index 86c3f3509a26..f0079e51d8d2 100644
--- a/drivers/iio/temperature/max31865.c
+++ b/drivers/iio/temperature/max31865.c
@@ -53,7 +53,7 @@  struct max31865_data {
 	struct mutex lock;
 	bool filter_50hz;
 	bool three_wire;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_DMA_MINALIGN);
 };
 
 static int max31865_read(struct max31865_data *data, u8 reg,