From patchwork Tue May 31 21:18:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12866169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59384C433EF for ; Tue, 31 May 2022 21:18:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347919AbiEaVSx (ORCPT ); Tue, 31 May 2022 17:18:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347921AbiEaVSu (ORCPT ); Tue, 31 May 2022 17:18:50 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AF1F5FF10; Tue, 31 May 2022 14:18:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654031927; x=1685567927; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5tfAedSxkAxJN42+QB7AqeZ7v7zfuJl7ab7/G0q0y9Y=; b=LPqe928HttUKC6csjyeTEidB+68JjP1xeIQHoJDlLk+rL384zTpiINQd PFh9APdQfNl++t7pvk8glRr4ISKrzvo4ayZk2poyXbS9FeQOKvvvZpFAx aSSTuFdMNe8yw3qk+fyaF7jviX+6zJI7vtJlk/b3CpEHVnuuaRvG9gjml SO+he+cwcHIFzjG2ogEmJXyQ1OSdalOBDfO53zLsbVIgkflAKQuN8DYnm rL+DQk0Z3xh867SAnxhR16dExGUPTrMTWMCyYpb3LkuHriaH9mLCBAG8J nn+zfPsq5aePtxNMeF2O6YXdB5ao080CGfYUhmssi6XpbwTaDmu+Sz2qj A==; X-IronPort-AV: E=McAfee;i="6400,9594,10364"; a="338432068" X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="338432068" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2022 14:18:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="529771625" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 31 May 2022 14:18:41 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id F2251D2; Wed, 1 Jun 2022 00:18:43 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Jonathan Cameron , Lars-Peter Clausen , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Subject: [PATCH v1 2/3] iio: adc: meson_saradc: Use devm_clk_get_optional() Date: Wed, 1 Jun 2022 00:18:41 +0300 Message-Id: <20220531211842.71998-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220531211842.71998-1-andriy.shevchenko@linux.intel.com> References: <20220531211842.71998-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Replace open coded variants of devm_clk_get_optional(). Signed-off-by: Andy Shevchenko Reviewed-by: Martin Blumenstingl --- drivers/iio/adc/meson_saradc.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index c2abbfc1396c..2fa384e59d28 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -1224,23 +1224,13 @@ static int meson_sar_adc_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); - priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); - if (IS_ERR(priv->adc_clk)) { - if (PTR_ERR(priv->adc_clk) == -ENOENT) - priv->adc_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk), - "failed to get adc clk\n"); - } + priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); + if (IS_ERR(priv->adc_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); - priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); - if (IS_ERR(priv->adc_sel_clk)) { - if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) - priv->adc_sel_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk), - "failed to get adc_sel clk\n"); - } + priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); + if (IS_ERR(priv->adc_sel_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ if (!priv->adc_clk) {