From patchwork Mon Jul 4 17:21:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Folkesson X-Patchwork-Id: 12905720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C5FAC43334 for ; Mon, 4 Jul 2022 17:19:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234604AbiGDRTi (ORCPT ); Mon, 4 Jul 2022 13:19:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234191AbiGDRTV (ORCPT ); Mon, 4 Jul 2022 13:19:21 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1B3BF3A; Mon, 4 Jul 2022 10:19:19 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id t19so16129398lfl.5; Mon, 04 Jul 2022 10:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A1ZkiED2+naYPTbg6tDbNhI0CZl87H54p76rxmGjur0=; b=Ha1Y2dyxxOT4DBC8XbeZFnWfynbiBmOAVZU+RTnbfh9ajcXuJHmxs8LnJ+puEHBFRg or7pgKmU6X2p+ReEpk+1Gaqdu6VBRBfNsTHxX99fJfD3fpDuftjOk+VMyE63uYytBfTi pB9qnn7fJGO5sm5Ta3twSZWyP4UsoVZNtJyOzNGt47B8pNz//dDct3elyVJ+Y+w2SgB0 FvIOGF9L36dQ/SiNkLg+F7Jp6ZO5owQxb1ZNnxiCilNjzRC+w0pZFNB88zzzPi10Io5E 0NTVgy9nSn7hdwMCsqjLxFyXDA3CnnVYgdhqTzZz6LA20z+T9b+P/Y5z72xSpbZ/wwEO zMnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A1ZkiED2+naYPTbg6tDbNhI0CZl87H54p76rxmGjur0=; b=oWj53RiNleAcyu8nSdn6kBhMHxOfsw9QX1ccQgpzfx93R2gXes/aFPJJK53cpaymjA OX5vhyjUfZkilCow4nOCj1sexY5W0Vqygse/bO233/B6Csx3tx6VtgxR9Oe9qCD962q4 FO+Sfe4VGAE3oikwtHNlQitjW7f49S0bhAI5j8hsr0GmbwrOzxtLpZKaRKqXvmLlN38u qR0VTQELYGt3LJGMTZh8OKUbAm5y0lpOtRlXT2qxMnEk/ZbKQqkQohftb0P9B+n+hUXU cqfzY0AD74ZfsC7e1m7Z3WAF5RvZNN610o7Q6prRMh49LWDU4T2vNpmbqUZveYZi3j1q 2Hlg== X-Gm-Message-State: AJIora/N/FsthxZk8TwwcQqDHxbPs8GEG2T7el7AB3Mr8VfmZ5gL0YGa P+IqffluKYnswO+ijQw13C0= X-Google-Smtp-Source: AGRyM1ur0m9Hod7r2mN8CTdCWJGjINIgT+1pmkFhPKv1ZFFK5n44oYzfKXTS1sUYTwGFKrS36CIsQw== X-Received: by 2002:a05:6512:61:b0:47f:7f37:fad3 with SMTP id i1-20020a056512006100b0047f7f37fad3mr20109181lfo.318.1656955157735; Mon, 04 Jul 2022 10:19:17 -0700 (PDT) Received: from localhost.localdomain (82-209-154-112.cust.bredband2.com. [82.209.154.112]) by smtp.gmail.com with ESMTPSA id v9-20020a2ea609000000b0025bf6099cdbsm2772720ljp.78.2022.07.04.10.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 10:19:17 -0700 (PDT) From: Marcus Folkesson To: Marcus Folkesson , Kent Gustavsson , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 8/9] iio: adc: mcp3911: add support for oversampling ratio Date: Mon, 4 Jul 2022 19:21:15 +0200 Message-Id: <20220704172116.195841-9-marcus.folkesson@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704172116.195841-1-marcus.folkesson@gmail.com> References: <20220704172116.195841-1-marcus.folkesson@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The chip supports oversampling ratio, so expose it to userspace. Signed-off-by: Marcus Folkesson --- drivers/iio/adc/mcp3911.c | 59 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/iio/adc/mcp3911.c b/drivers/iio/adc/mcp3911.c index 9c6f456bdbdf..c6e30471bb81 100644 --- a/drivers/iio/adc/mcp3911.c +++ b/drivers/iio/adc/mcp3911.c @@ -38,6 +38,7 @@ #define MCP3911_REG_CONFIG 0x0c #define MCP3911_CONFIG_CLKEXT BIT(1) #define MCP3911_CONFIG_VREFEXT BIT(2) +#define MCP3911_CONFIG_OSR GENMASK(13, 11) #define MCP3911_REG_OFFCAL_CH0 0x0e #define MCP3911_REG_GAINCAL_CH0 0x11 @@ -56,6 +57,8 @@ #define MCP3911_NUM_CHANNELS 2 +static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; + struct mcp3911 { struct spi_device *spi; struct mutex lock; @@ -114,6 +117,36 @@ static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, return mcp3911_write(adc, reg, val, len); } +static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return IIO_VAL_INT; + default: + return IIO_VAL_INT_PLUS_NANO; + } +} + +static int mcp3911_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *type = IIO_VAL_INT; + *vals = mcp3911_osr_table; + *length = ARRAY_SIZE(mcp3911_osr_table); + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + static int mcp3911_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int *val, int *val2, long mask) @@ -142,6 +175,16 @@ static int mcp3911_read_raw(struct iio_dev *indio_dev, ret = IIO_VAL_INT; break; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret = mcp3911_read(adc, + MCP3911_REG_CONFIG, val, 2); + if (ret) + goto out; + + *val = FIELD_GET(MCP3911_CONFIG_OSR, *val); + *val = 32 << *val; + ret = IIO_VAL_INT; + break; case IIO_CHAN_INFO_SCALE: if (adc->vref) { @@ -201,6 +244,17 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev, MCP3911_STATUSCOM_EN_OFFCAL, MCP3911_STATUSCOM_EN_OFFCAL, 2); break; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + for (int i = 0; i < sizeof(mcp3911_osr_table); i++) { + if (val == mcp3911_osr_table[i]) { + val = FIELD_PREP(MCP3911_CONFIG_OSR, i); + ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR, + val, 2); + break; + } + } + break; } out: @@ -213,9 +267,12 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev, .indexed = 1, \ .channel = idx, \ .scan_index = idx, \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_OFFSET) | \ BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .scan_type = { \ .sign = 's', \ .realbits = 24, \ @@ -275,6 +332,8 @@ static irqreturn_t mcp3911_trigger_handler(int irq, void *p) static const struct iio_info mcp3911_info = { .read_raw = mcp3911_read_raw, .write_raw = mcp3911_write_raw, + .read_avail = mcp3911_read_avail, + .write_raw_get_fmt = mcp3911_write_raw_get_fmt, }; static int mcp3911_config(struct mcp3911 *adc)