From patchwork Wed Oct 5 16:14:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Moysan X-Patchwork-Id: 12999434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB22DC433FE for ; Wed, 5 Oct 2022 16:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbiJEQQo (ORCPT ); Wed, 5 Oct 2022 12:16:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230482AbiJEQQV (ORCPT ); Wed, 5 Oct 2022 12:16:21 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58D797DF78; Wed, 5 Oct 2022 09:16:15 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 295C4Wkk004431; Wed, 5 Oct 2022 18:15:52 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=yc8TFrk/Tb/1WdSjthFD7CUlEtaWtaDiWSfbevdc6vw=; b=nVJ28PYz4zzdsQGZSGZsSU3n6ywbJGyq8tf910sYBrNqU4yCb+9RSk+gQDeBvbhEt/Ie ugpikQWaKhCSkmPWpRqalHf/ml5fzYowet6earJZK15+3goIyE1GNVjnkpnUe8eoIOJP dEyd8yF2CfvQ++EdU3Iwp3aNN+plLMMVRqKJJo8A8sF6M7evVrg9yYsyu7AH0+Rvr/TY nIvIaLON3RRiTHYKHx+cyQ7u0DsksIRsnvTiBvPqgSfa94c0Oo3eLweuHBag6KGueQSY WmBLHZBgJlio/FiI+nm+99XLzPTcEGkCvWojqBFiBwEaEOIjfFeaFqqwcZUBjdDgVtvf Eg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jxaym8q9u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 18:15:52 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DB843100034; Wed, 5 Oct 2022 18:15:46 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D5E0D235F14; Wed, 5 Oct 2022 18:15:46 +0200 (CEST) Received: from localhost (10.75.127.45) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Wed, 5 Oct 2022 18:15:46 +0200 From: Olivier Moysan To: Alexandre Torgue , Andy Shevchenko , Fabrice Gasnier , Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , , Olivier Moysan , Paul Cercueil , Sebastian Andrzej Siewior , Wan Jiabing , Yannick Brosseau CC: , , , Subject: [PATCH v3 6/8] ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk Date: Wed, 5 Oct 2022 18:14:22 +0200 Message-ID: <20221005161424.4537-7-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221005161424.4537-1-olivier.moysan@foss.st.com> References: <20221005161424.4537-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-05_03,2022-10-05_01,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Define pins muxing that can be used for ADC on stm32mp135f-dk board (USB Type-C CC1 & CC2 pins). Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index d2472cd8f1d0..9cd58bf54ac8 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,13 @@ #include &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC1 in12 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */