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[90.5.9.60]) by smtp.gmail.com with ESMTPSA id q11-20020adffecb000000b003332db7d91dsm18421015wrs.39.2023.12.15.02.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 02:32:10 -0800 (PST) From: David Lechner To: linux-iio@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Cc: David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: spi: add spi-rx-bus-channels peripheral property Date: Fri, 15 Dec 2023 04:32:02 -0600 Message-Id: <20231215-ad7380-mainline-v3-1-7a11ebf642b9@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> References: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new spi-rx-bus-channels property to the generic spi peripheral property bindings. This property is used to describe devices that have parallel data output channels. This property is different from spi-rx-bus-width in that the latter means that we are reading multiple bits of a single word at one time while the former means that we are reading single bits of multiple words at the same time. Signed-off-by: David Lechner Reviewed-by: Rob Herring --- The rest of this series is ready to merge, so just looking for an ack from Mark on this one. .../devicetree/bindings/spi/spi-peripheral-props.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 15938f81fdce..1c8e71c18234 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -67,6 +67,18 @@ properties: enum: [0, 1, 2, 4, 8] default: 1 + spi-rx-bus-channels: + description: + The number of parallel channels for read transfers. The difference between + this and spi-rx-bus-width is that a value N for spi-rx-bus-channels means + the SPI bus is receiving one bit each of N different words at the same + time whereas a value M for spi-rx-bus-width means that the bus is + receiving M bits of a single word at the same time. It is also possible to + use both properties at the same time, meaning the bus is receiving M bits + of N different words at the same time. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer.