@@ -42,6 +42,9 @@
#define ADI_AXI_ADC_REG_CTRL 0x0044
#define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1)
+#define ADI_AXI_ADC_REG_DRP_STATUS 0x0074
+#define ADI_AXI_ADC_DRP_LOCKED BIT(17)
+
/* ADC Channel controls */
#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
@@ -83,6 +86,7 @@ struct adi_axi_adc_state {
static int axi_adc_enable(struct iio_backend *back)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
+ unsigned int __val;
int ret;
guard(mutex)(&st->lock);
@@ -91,7 +95,17 @@ static int axi_adc_enable(struct iio_backend *back)
if (ret)
return ret;
- fsleep(10000);
+ /*
+ * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
+ * designs really use it but if they don't we still get the lock bit
+ * set. So let's do it all the time so the code is generic.
+ */
+ ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS,
+ __val, __val & ADI_AXI_ADC_DRP_LOCKED,
+ 100, 1000);
+ if (ret)
+ return ret;
+
return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,
ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
}