Message ID | 20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-5-ceb157487329@baylibre.com (mailing list archive) |
---|---|
State | Changes Requested |
Headers | show |
Series | iio: add support for the ad3552r AXI DAC IP | expand |
On Thu, Oct 03, 2024 at 07:29:02PM +0200, Angelo Dureghello wrote: > From: Angelo Dureghello <adureghello@baylibre.com> > > There is a version of AXI DAC IP block (for FPGAs) that provides > a physical QSPI bus for AD3552R and similar chips, so supporting > spi-controller functionalities. > > For this case, the binding is modified to include some additional > properties. > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 41fe00034742..2d2561a52683 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -60,6 +60,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + io-backends: + description: The iio backend reference. + Device can be optionally connected to the "axi-ad3552r IP" fpga-based + QSPI + DDR (Double Data Rate) controller to reach high speed transfers. + maxItems: 1 + '#address-cells': const: 1 @@ -128,6 +134,7 @@ patternProperties: - custom-output-range-config allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: