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[79.41.194.153]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431935f6df1sm12895085e9.35.2024.10.25.02.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 02:50:55 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Fri, 25 Oct 2024 11:49:34 +0200 Subject: [PATCH v8 1/8] dt-bindings: iio: dac: ad3552r: add iio backend support Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-1-74ca7dd60567@baylibre.com> References: <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-0-74ca7dd60567@baylibre.com> In-Reply-To: <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-0-74ca7dd60567@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , dlechner@baylibre.com, Angelo Dureghello , Conor Dooley X-Mailer: b4 0.14.1 From: Angelo Dureghello There is a version of AXI DAC IP block (for FPGAs) that provides a physical QSPI bus for AD3552R and similar chips, so supporting spi-controller functionalities. For this case, the binding is modified to include some additional properties. Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 41fe00034742..2d2561a52683 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -60,6 +60,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + io-backends: + description: The iio backend reference. + Device can be optionally connected to the "axi-ad3552r IP" fpga-based + QSPI + DDR (Double Data Rate) controller to reach high speed transfers. + maxItems: 1 + '#address-cells': const: 1 @@ -128,6 +134,7 @@ patternProperties: - custom-output-range-config allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: