diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h
index 4ba493f636..c9d2a82fa6 100644
--- a/drivers/iio/accel/adxl345.h
+++ b/drivers/iio/accel/adxl345.h
@@ -8,38 +8,9 @@
 #ifndef _ADXL345_H_
 #define _ADXL345_H_
 
-#define ADXL345_REG_DEVID		0x00
-#define ADXL345_REG_OFSX		0x1E
-#define ADXL345_REG_OFSY		0x1F
-#define ADXL345_REG_OFSZ		0x20
-#define ADXL345_REG_OFS_AXIS(index)	(ADXL345_REG_OFSX + (index))
-#define ADXL345_REG_BW_RATE		0x2C
-#define ADXL345_REG_POWER_CTL		0x2D
-#define ADXL345_REG_DATA_FORMAT		0x31
-#define ADXL345_REG_DATAX0		0x32
-#define ADXL345_REG_DATAY0		0x34
-#define ADXL345_REG_DATAZ0		0x36
-#define ADXL345_REG_DATA_AXIS(index)	\
-	(ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
-
-#define ADXL345_BW_RATE			GENMASK(3, 0)
-#define ADXL345_BASE_RATE_NANO_HZ	97656250LL
-
-#define ADXL345_POWER_CTL_MEASURE	BIT(3)
-#define ADXL345_POWER_CTL_STANDBY	0x00
-
-#define ADXL345_DATA_FORMAT_RANGE	GENMASK(1, 0)	/* Set the g range */
-#define ADXL345_DATA_FORMAT_JUSTIFY	BIT(2)	/* Left-justified (MSB) mode */
-#define ADXL345_DATA_FORMAT_FULL_RES	BIT(3)	/* Up to 13-bits resolution */
+/* Regs and bits needed to be declared globally */
+#define ADXL345_REG_DATA_FORMAT		0x31 /* r/w  Data format control */
 #define ADXL345_DATA_FORMAT_SPI_3WIRE	BIT(6)	/* 3-wire SPI mode */
-#define ADXL345_DATA_FORMAT_SELF_TEST	BIT(7)	/* Enable a self test */
-
-#define ADXL345_DATA_FORMAT_2G		0
-#define ADXL345_DATA_FORMAT_4G		1
-#define ADXL345_DATA_FORMAT_8G		2
-#define ADXL345_DATA_FORMAT_16G		3
-
-#define ADXL345_DEVID			0xE5
 
 /*
  * In full-resolution mode, scale factor is maintained at ~4 mg/LSB
diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
index ef3b7d9fb4..aac49b3d03 100644
--- a/drivers/iio/accel/adxl345_core.c
+++ b/drivers/iio/accel/adxl345_core.c
@@ -18,6 +18,114 @@
 
 #include "adxl345.h"
 
+/* ADXL345 register map */
+#define ADXL345_REG_DEVID		0x00 /* r    Device ID */
+#define ADXL345_REG_THRESH_TAP	0x1D /* r/w  Tap Threshold */
+#define ADXL345_REG_OFSX		0x1E /* r/w  X-axis offset */
+#define ADXL345_REG_OFSY		0x1F /* r/w  Y-axis offset */
+#define ADXL345_REG_OFSZ		0x20 /* r/w  Z-axis offset */
+#define ADXL345_REG_DUR		0x21 /* r/w  Tap duration */
+#define ADXL345_REG_LATENT		0x22 /* r/w  Tap latency */
+#define ADXL345_REG_WINDOW		0x23 /* r/w  Tap window */
+#define ADXL345_REG_THRESH_ACT		0x24 /* r/w  Activity threshold */
+#define ADXL345_REG_THRESH_INACT	0x25 /* r/w  Inactivity threshold */
+#define ADXL345_REG_TIME_INACT	0x26 /* r/w  Inactivity time */
+#define ADXL345_REG_ACT_INACT_CTRL	0x27 /* r/w  Axis enable control for */
+					     /*      activity and inactivity */
+					     /*      detection */
+#define ADXL345_REG_THRESH_FF		0x28 /* r/w  Free-fall threshold */
+#define ADXL345_REG_TIME_FF		0x29 /* r/w  Free-fall time */
+#define ADXL345_REG_TAP_AXIS		0x2A /* r/w  Axis control for */
+					     /*      single tap or double tap */
+#define ADXL345_REG_ACT_TAP_STATUS	0x2B /* r    Source of single tap or */
+					     /*      double tap */
+#define ADXL345_REG_BW_RATE		0x2C /* r/w  Data rate and power */
+					     /*        mode control */
+#define ADXL345_REG_POWER_CTL		0x2D /* r/w  Power-saving features */
+#define ADXL345_REG_INT_ENABLE		0x2E /* r/w  Interrupt enable control */
+#define ADXL345_REG_INT_MAP		0x2F /* r/w  Interrupt mapping */
+					     /*      control */
+#define ADXL345_REG_INT_SOURCE		0x30 /* r    Source of interrupts */
+/* NB: ADXL345_REG_DATA_FORMAT		0x31  r/w  Data format control,
+ *   (defined in header)
+ */
+
+#define ADXL345_REG_XYZ_BASE		0x32 /* r    Base address to read out */
+					     /*      X-, Y- and Z-axis data 0 */
+					     /*      and 1 */
+#define ADXL345_REG_DATA_AXIS(index)				\
+	(ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16))
+/* NB: having DATAX0 and DATAX1 makes 2x sizeof(__le16) */
+
+#define ADXL345_REG_FIFO_CTL		0x38 /* r/w  FIFO control */
+#define ADXL345_REG_FIFO_STATUS		0x39 /* r    FIFO status */
+
+/* DEVID(s) */
+#define ADXL345_DEVID			0xE5
+
+/* FIFO */
+#define ADXL345_FIFO_CTL_SAMLPES(x)	(0x1f & (x))
+#define ADXL345_FIFO_CTL_TRIGGER(x)	(0x20 & ((x) << 5)) /* set 1: INT2, 0: INT1 */
+#define ADXL345_FIFO_CTL_MODE(x)	(0xc0 & ((x) << 6))
+
+/* INT_ENABLE, INT_MAP, INT_SOURCE bits */
+#define ADXL345_INT_DATA_READY		BIT(7)
+#define ADXL345_INT_SINGLE_TAP		BIT(6)
+#define ADXL345_INT_DOUBLE_TAP		BIT(5)
+#define ADXL345_INT_ACTIVITY		BIT(4)
+#define ADXL345_INT_INACTIVITY		BIT(3)
+#define ADXL345_INT_FREE_FALL		BIT(2)
+#define ADXL345_INT_WATERMARK		BIT(1)
+#define ADXL345_INT_OVERRUN		BIT(0)
+
+#define ADXL34X_S_TAP_MSK	ADXL345_INT_SINGLE_TAP
+#define ADXL34X_D_TAP_MSK	ADXL345_INT_DOUBLE_TAP
+
+/* INT1 or INT2 */
+#define ADXL345_INT1			0
+#define ADXL345_INT2			1
+
+/* BW_RATE bits - Bandwidth and output data rate. The default value is
+ * 0x0A, which translates to a 100 Hz output data rate
+ */
+#define ADXL345_BW_RATE			GENMASK(3, 0)
+#define ADXL345_BW_LOW_POWER	BIT(4)
+#define ADXL345_BASE_RATE_NANO_HZ	97656250LL
+
+/* POWER_CTL bits */
+#define ADXL345_POWER_CTL_STANDBY	0x00
+
+/* NB:
+ * BIT(0), BIT(1) for explicit wakeup (not implemented)
+ * BIT(2) for explicit sleep (not implemented)
+ */
+#define ADXL345_POWER_CTL_MEASURE	BIT(3)
+#define ADXL345_POWER_CTL_AUTO_SLEEP	BIT(4)
+#define ADXL345_POWER_CTL_LINK	BIT(5)
+
+/* DATA_FORMAT bits */
+#define ADXL345_DATA_FORMAT_RANGE	GENMASK(1, 0)	/* Set the g range */
+#define ADXL345_DATA_FORMAT_JUSTIFY	BIT(2)	/* 1: left-justified (MSB) mode, 0: right-just'd */
+#define ADXL345_DATA_FORMAT_FULL_RES	BIT(3)	/* Up to 13-bits resolution */
+/* NB: BIT(6): 3-wire SPI mode (defined in header) */
+
+#define ADXL345_DATA_FORMAT_SELF_TEST	BIT(7)	/* Enable a self test */
+#define ADXL345_DATA_FORMAT_2G		0
+#define ADXL345_DATA_FORMAT_4G		1
+#define ADXL345_DATA_FORMAT_8G		2
+#define ADXL345_DATA_FORMAT_16G		3
+
+#define ADXL345_REG_OFS_AXIS(index)	(ADXL345_REG_OFSX + (index))
+
+/* The ADXL345 include a 32 sample FIFO
+ *
+ * FIFO stores a maximum of 32 entries, which equates to a maximum of 33
+ * entries available at any given time because an additional entry is available
+ * at the output filter of the device.
+ * (see datasheet FIFO_STATUS description on "Entries Bits")
+ */
+#define ADXL34x_FIFO_SIZE  33
+
 struct adxl34x_state {
 	int irq;
 	const struct adxl345_chip_info *info;
