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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3823f72441bsm3028137f8f.101.2024.11.17.10.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2024 10:28:32 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v2 17/22] iio: accel: adxl345: push FIFO data to iio Date: Sun, 17 Nov 2024 18:26:46 +0000 Message-Id: <20241117182651.115056-18-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241117182651.115056-1-l.rubusch@gmail.com> References: <20241117182651.115056-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add FIFO and hwfifo handling. Add some functions to deal with FIFO entries and configuration. This feature will be needed for e.g. watermark setting. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index d58e1994ff..a653774db8 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -437,6 +437,41 @@ static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat) return 0; } +static int adxl345_push_fifo_data(struct iio_dev *indio_dev, + u8 status, + int fifo_entries) +{ + struct adxl34x_state *st = iio_priv(indio_dev); + int ndirs = 3; /* 3 directions */ + int i, ret; + + if (fifo_entries <= 0) + return true; + + ret = adxl345_read_fifo_elements(st, fifo_entries); + if (ret) + return false; + + for (i = 0; i < ndirs * fifo_entries; i += ndirs) { + /* To ensure that the FIFO has completely popped, there must be at least 5 + * us between the end of reading the data registers, signified by the + * transition to register 0x38 from 0x37 or the CS pin going high, and the + * start of new reads of the FIFO or reading the FIFO_STATUS register. For + * SPI operation at 1.5 MHz or lower, the register addressing portion of the + * transmission is sufficient delay to ensure the FIFO has completely + * popped. It is necessary for SPI operation greater than 1.5 MHz to + * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us + * at 5 MHz operation. + */ + if (st->fifo_delay && (fifo_entries > 1)) + udelay(3); + + iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); + } + + return true; +} + /* data ready trigger */ static int adxl345_trig_dready(struct iio_trigger *trig, bool state) @@ -508,6 +543,9 @@ static irqreturn_t adxl345_trigger_handler(int irq, void *p) if (adxl345_get_fifo_entries(st, &fifo_entries) < 0) goto err; + if (adxl345_push_fifo_data(indio_dev, int_stat, fifo_entries) < 0) + goto err; + iio_trigger_notify_done(indio_dev->trig); }