From patchwork Wed Mar 5 09:49:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 14002234 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7000E2063F2; Wed, 5 Mar 2025 09:54:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741168454; cv=none; b=XIwF1vtZy1d7cJbfbw1BOugNoc5wma3APsTPFFxeIfclOiFN6cJLNJ8f2f/UEr3z3bqNEYoEXYDPyzEoguB9JBnMPndBG1jJdUIFbsNAKXN7TDiXDXfIjvQDAkGb/tfWxfOLUi2YZVgLmwWbjfJK6Lvhd/X8aKJefV9gfVtxlu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741168454; c=relaxed/simple; bh=9FU/7m3L6w46a3y3tZQoZf0uV5nbJVVfFNXKFyOuXOs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LI1iG0DOMLFZ9m87JWqZoFcsjI4Rhb/adio0o1kpCe9+Vvt8k1oZPdSCE32lzBH/Nag1Y/MCMUQ6gHVsmAL7sRDA3WVfNse9bMh8yno39TS+9XA/Q3k7eeg3IietIeVNVhnQ79evANC70PPg/cZJoFVpijEl+noU3LC4h2b/icI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=4yYu27+H; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="4yYu27+H" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5258h91S026811; Wed, 5 Mar 2025 10:53:58 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= HPWXN7XU6ij/VILhA4L2prDYWt4HSSzxWCxw+iSrXQ4=; b=4yYu27+H0FZ0o41k cM7xAskr/IDPManubEqf90BwrtoDEgyArDs68oLfUOmtLpELAbvSBV9hobiLZxK9 MetDWmT98iHVAAQsjMowciE2J5VAHFwnYfYLmvl1EK5u4KcLVGBChTMgs4EcWJoE p1j1pfMbQqqt1Rl9C0QLXkWCiJYiq2tGTJKvMkCzWN/lPygiOu1vrvkUBdPiqIMy oqMUmgT1uLak+l0NNQy1g58PZUMpttiBq7GnvKIRzow5MyIettcMznFXlH3x0942 z+gcKMH8gIQewG5qd5XZUUV1fXhuCbeQL0LtyUuiiU54JgpXG5fZnWbdyw959d4G giSBJg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 453t83kqpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Mar 2025 10:53:58 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BA28B40045; Wed, 5 Mar 2025 10:52:53 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E27BA5A9E13; Wed, 5 Mar 2025 10:49:55 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:55 +0100 Received: from localhost (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:55 +0100 From: Fabrice Gasnier To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v3 6/8] arm64: defconfig: enable STM32 LP timer clockevent driver Date: Wed, 5 Mar 2025 10:49:33 +0100 Message-ID: <20250305094935.595667-7-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> References: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-05_03,2025-03-05_01,2024-11-22_01 Enable the STM32 LP timer MFD core and clockevent drivers used on STM32MP257F-EV1 board, for PSCI OSI. Signed-off-by: Fabrice Gasnier --- Changes in v2: - dropped unused IIO trigger, PWM and counter driver unused on upstream board currently, as advised by Krzysztof --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1f25423de383..b29b2350ae27 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -775,6 +775,7 @@ CONFIG_MFD_TI_LP873X=m CONFIG_MFD_TPS65219=y CONFIG_MFD_TPS6594_I2C=m CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_STM32_LPTIMER=m CONFIG_MFD_WCD934X=m CONFIG_MFD_KHADAS_MCU=m CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -1401,6 +1402,7 @@ CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y +CONFIG_CLKSRC_STM32_LP=y CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y