diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 7a2da7f..cede523 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -57,7 +57,7 @@
 #define MMA8452_FF_MT_THS            0x17
 #define  MMA8452_FF_MT_THS_MASK            0x7f
 #define MMA8452_FF_MT_COUNT            0x18
-#define MMA8452_FF_MT_CHAN_SHIFT    3
+#define MMA8452_FF_MT_CHAN_SHIFT        3
 #define MMA8452_TRANSIENT_CFG            0x1d
 #define  MMA8452_TRANSIENT_CFG_CHAN(chan)    BIT(chan + 1)
 #define  MMA8452_TRANSIENT_CFG_HPF_BYP        BIT(0)
@@ -69,7 +69,7 @@
 #define MMA8452_TRANSIENT_THS            0x1f
 #define  MMA8452_TRANSIENT_THS_MASK        GENMASK(6, 0)
 #define MMA8452_TRANSIENT_COUNT            0x20
-#define MMA8452_TRANSIENT_CHAN_SHIFT 1
+#define MMA8452_TRANSIENT_CHAN_SHIFT        1
 #define MMA8452_CTRL_REG1            0x2a
 #define  MMA8452_CTRL_ACTIVE            BIT(0)
 #define  MMA8452_CTRL_DR_MASK            GENMASK(5, 3)
@@ -106,6 +106,7 @@ struct mma8452_data {
     u8 ctrl_reg1;
     u8 data_cfg;
     const struct mma_chip_info *chip_info;
+    int sleep_val;
 };
 
  /**
@@ -193,7 +194,10 @@ static int mma8452_drdy(struct mma8452_data *data)
         if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
             return 0;
 
-        msleep(20);
+        if (data->sleep_val <= 20)
+            usleep_range(data->sleep_val * 250, data->sleep_val * 500);
+        else
+            msleep(20);
     }
 
     dev_err(&data->client->dev, "data not ready\n");
@@ -544,10 +548,22 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
     return -EINVAL;
 }
 
+static int mma8452_calculate_sleep(struct mma8452_data *data)
+{
+    int ret, i = mma8452_get_odr_index(data);
+  
+    if (mma8452_samp_freq[i][0] > 0)
+        ret = 1000 / mma8452_samp_freq[i][0];
+    else
+        ret = 1000;
+
+    return ret == 0 ? 1 : ret;
+}
+
 static int mma8452_standby(struct mma8452_data *data)
 {
     return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
-                    data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
+                     data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
 }
 
 static int mma8452_active(struct mma8452_data *data)
@@ -700,6 +716,8 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
         data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
         data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
 
+        data->sleep_val = mma8452_calculate_sleep(data);
+
         ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
                         data->ctrl_reg1);
         break;
@@ -738,7 +756,7 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
         }
 
         ret = mma8452_change_config(data, MMA8452_DATA_CFG,
-                         data->data_cfg);
+                        data->data_cfg);
         break;
 
     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
@@ -761,8 +779,9 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
 }
 
 static int mma8452_get_event_regs(struct mma8452_data *data,
-        const struct iio_chan_spec *chan, enum iio_event_direction dir,
-        const struct mma8452_event_regs **ev_reg)
+                  const struct iio_chan_spec *chan,
+                  enum iio_event_direction dir,
+                  const struct mma8452_event_regs **ev_reg)
 {
     if (!chan)
         return -EINVAL;
@@ -772,9 +791,9 @@ static int mma8452_get_event_regs(struct
mma8452_data *data,
         switch (dir) {
         case IIO_EV_DIR_RISING:
             if ((data->chip_info->all_events
-                    & MMA8452_INT_TRANS) &&
-                (data->chip_info->enabled_events
-                    & MMA8452_INT_TRANS))
+                & MMA8452_INT_TRANS) &&
+                (data->chip_info->enabled_events
+                & MMA8452_INT_TRANS))
                 *ev_reg = &trans_ev_regs;
             else
