From patchwork Wed May 16 17:52:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 10404535 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 734DC60155 for ; Wed, 16 May 2018 17:52:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6046428595 for ; Wed, 16 May 2018 17:52:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5487E285ED; Wed, 16 May 2018 17:52:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5EC3428595 for ; Wed, 16 May 2018 17:52:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752325AbeEPRwP (ORCPT ); Wed, 16 May 2018 13:52:15 -0400 Received: from mail-yb0-f193.google.com ([209.85.213.193]:46868 "EHLO mail-yb0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752317AbeEPRwN (ORCPT ); Wed, 16 May 2018 13:52:13 -0400 Received: by mail-yb0-f193.google.com with SMTP id f3-v6so549717ybg.13; Wed, 16 May 2018 10:52:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f3zch8sNGAbyhEIi0UH9KhG1Sk/tkqlsFYDR79YJGnQ=; b=J0//0hD3EGTM6wBUSP3rY0hpePLIPFu7M4kOs+uHsG6qINsN4n57/9GrwlBYoaBPoD /FPz8OmZVyG0lz2xlZ8wv5BJbtqVfYkbQA3pEXb//TKBZXeBYeRhxchgrpQk8dr/m7Ch IyiLIqqkMjNQqLWexv70gyCP6tjCvl1wpX95AEw6Wwz+sL4Cw6pp8/ak65YHvVfuSTRT I7mar5V0ZRiFz0WlNXDqBT200AZo+pbyVCF9ZYfAPElXOF30emUa0aJZPFmJpm1xknCC b27WncK6+M32zE2rGMQlkXLWfs7i2Pdgp0ESv/PP2+/9QF7wxEO2z2e+3aECWkGCBKW0 DWdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f3zch8sNGAbyhEIi0UH9KhG1Sk/tkqlsFYDR79YJGnQ=; b=j9YSpm9Z7YpabkkPMepW/NWRl+NnDTDn/t5FYTGS2zxMrvRZ1lXsP4u2TcfTH7d3Fd NITW6UKMdw9DDl5Oeh6LEvq27tyzIGTJWP23dAbxpFYvPPO9lfxnZpyhSjQbl8Lj/oCQ 2d6gg2BFiheiDl6vQEnLs7QAQTjTKClZiKiDvMI3gkNVgMDngvfKzqUvX08P007TTMen /vMZ3gFzaqWb7+j1LLcOB4LWFMyfTpHT84GEQIVhcu23neIWCy4n/4CdWl/vNN2xYXsR VjsXox1+pwZBiqTYCAGVK38ULLwY3BDmpik3BwaiB74oD7in/muQ8NSh+IPnJGL+zYcg MkOQ== X-Gm-Message-State: ALKqPwcjOrJqy56qmqjKPeFWMCEsPJQJ/fT0v7ytrOlFvCPjIecOs2VY On1Tqhbckdcb7Tf8/HEzYBo= X-Google-Smtp-Source: AB8JxZp5DF/SZ8+Tw5EFbF+fDPXWJ8JCqwVhxFj0no3tIfk9fbjM0oNzK0qCe/A61qXkzLCDE1r1AQ== X-Received: by 2002:a25:ae1b:: with SMTP id a27-v6mr1079322ybj.62.1526493132942; Wed, 16 May 2018 10:52:12 -0700 (PDT) Received: from localhost ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id k2-v6sm642108ywi.18.2018.05.16.10.52.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 10:52:12 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: benjamin.gaignard@st.com, fabrice.gasnier@st.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, William Breathitt Gray Subject: [PATCH v6 7/9] counter: Add STM32 Timer quadrature encoder Date: Wed, 16 May 2018 13:52:06 -0400 Message-Id: <3ef3720286d95ddc8205f31d3489fff474bd1cbb.1526487615.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: References: Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Gaignard Implement counter part of the STM32 timer hardware block by using counter API. Hardware only supports X2 and X4 quadrature modes. A ceiling value can be set to define the maximum value reachable by the counter. Signed-off-by: Benjamin Gaignard Co-authored-by: Fabrice Gasnier Signed-off-by: William Breathitt Gray --- drivers/counter/Kconfig | 10 + drivers/counter/Makefile | 1 + drivers/counter/stm32-timer-cnt.c | 390 ++++++++++++++++++++++++++++++ 3 files changed, 401 insertions(+) create mode 100644 drivers/counter/stm32-timer-cnt.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 73f03372484f..90b698aa52cf 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -36,4 +36,14 @@ config 104_QUAD_8 The base port addresses for the devices may be configured via the base array module parameter. +config STM32_TIMER_CNT + tristate "STM32 Timer encoder counter driver" + depends on MFD_STM32_TIMERS || COMPILE_TEST + help + Select this option to enable STM32 Timer quadrature encoder + and counter driver. + + To compile this driver as a module, choose M here: the + module will be called stm32-timer-cnt. + endif # COUNTER diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index 23a4f6263e45..ff024259fb46 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_COUNTER) += counter.o counter-y := generic-counter.o obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o +obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c new file mode 100644 index 000000000000..8fc6f74751b0 --- /dev/null +++ b/drivers/counter/stm32-timer-cnt.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32 Timer Encoder and Counter driver + * + * Copyright (C) STMicroelectronics 2018 + * + * Author: Benjamin Gaignard + * + */ +#include +#include +#include +#include +#include +#include + +#define TIM_CCMR_CCXS (BIT(8) | BIT(0)) +#define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \ + TIM_CCMR_IC1F | TIM_CCMR_IC2F) +#define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ + TIM_CCER_CC2P | TIM_CCER_CC2NP) + +struct stm32_timer_cnt { + struct counter_device counter; + struct regmap *regmap; + struct clk *clk; + u32 ceiling; +}; + +/** + * stm32_count_function - enumerates stm32 timer counter encoder modes + * @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1 + * @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level + * @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level + * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges + */ +enum stm32_count_function { + STM32_COUNT_SLAVE_MODE_DISABLED = -1, + STM32_COUNT_ENCODER_MODE_1, + STM32_COUNT_ENCODER_MODE_2, + STM32_COUNT_ENCODER_MODE_3, +}; + +static enum count_function stm32_count_functions[] = { + [STM32_COUNT_ENCODER_MODE_1] = COUNT_FUNCTION_QUADRATURE_X2_A, + [STM32_COUNT_ENCODER_MODE_2] = COUNT_FUNCTION_QUADRATURE_X2_B, + [STM32_COUNT_ENCODER_MODE_3] = COUNT_FUNCTION_QUADRATURE_X4, +}; + +static int stm32_count_read(struct counter_device *counter, + struct counter_count *count, + struct count_read_value *val) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 cnt; + + regmap_read(priv->regmap, TIM_CNT, &cnt); + set_count_read_value(val, COUNT_POSITION_UNSIGNED, &cnt); + + return 0; +} + +static int stm32_count_write(struct counter_device *counter, + struct counter_count *count, + struct count_write_value *val) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 cnt; + int err; + + err = get_count_write_value(&cnt, COUNT_POSITION_UNSIGNED, val); + if (err) + return err; + + if (cnt > priv->ceiling) + return -EINVAL; + + return regmap_write(priv->regmap, TIM_CNT, cnt); +} + +static int stm32_count_function_get(struct counter_device *counter, + struct counter_count *count, + size_t *function) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 smcr; + + regmap_read(priv->regmap, TIM_SMCR, &smcr); + + switch (smcr & TIM_SMCR_SMS) { + case 1: + *function = STM32_COUNT_ENCODER_MODE_1; + return 0; + case 2: + *function = STM32_COUNT_ENCODER_MODE_2; + return 0; + case 3: + *function = STM32_COUNT_ENCODER_MODE_3; + return 0; + } + + return -EINVAL; +} + +static int stm32_count_function_set(struct counter_device *counter, + struct counter_count *count, + size_t function) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 cr1, sms; + + switch (function) { + case STM32_COUNT_ENCODER_MODE_1: + sms = 1; + break; + case STM32_COUNT_ENCODER_MODE_2: + sms = 2; + break; + case STM32_COUNT_ENCODER_MODE_3: + sms = 3; + break; + default: + sms = 0; + break; + } + + /* Store enable status */ + regmap_read(priv->regmap, TIM_CR1, &cr1); + + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + + /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); + regmap_write(priv->regmap, TIM_ARR, priv->ceiling); + + regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); + + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + + /* Restore the enable status */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1); + + return 0; +} + +static ssize_t stm32_count_direction_read(struct counter_device *counter, + struct counter_count *count, + void *private, char *buf) +{ + struct stm32_timer_cnt *const priv = counter->priv; + const char *direction; + u32 cr1; + + regmap_read(priv->regmap, TIM_CR1, &cr1); + direction = (cr1 & TIM_CR1_DIR) ? "backward" : "forward"; + + return scnprintf(buf, PAGE_SIZE, "%s\n", direction); +} + +static ssize_t stm32_count_ceiling_read(struct counter_device *counter, + struct counter_count *count, + void *private, char *buf) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 arr; + + regmap_read(priv->regmap, TIM_ARR, &arr); + + return snprintf(buf, PAGE_SIZE, "%u\n", arr); +} + +static ssize_t stm32_count_ceiling_write(struct counter_device *counter, + struct counter_count *count, + void *private, + const char *buf, size_t len) +{ + struct stm32_timer_cnt *const priv = counter->priv; + unsigned int ceiling; + int ret; + + ret = kstrtouint(buf, 0, &ceiling); + if (ret) + return ret; + + /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); + regmap_write(priv->regmap, TIM_ARR, ceiling); + + priv->ceiling = ceiling; + return len; +} + +static ssize_t stm32_count_enable_read(struct counter_device *counter, + struct counter_count *count, + void *private, char *buf) +{ + struct stm32_timer_cnt *const priv = counter->priv; + u32 cr1; + + regmap_read(priv->regmap, TIM_CR1, &cr1); + + return scnprintf(buf, PAGE_SIZE, "%d\n", (bool)(cr1 & TIM_CR1_CEN)); +} + +static ssize_t stm32_count_enable_write(struct counter_device *counter, + struct counter_count *count, + void *private, + const char *buf, size_t len) +{ + struct stm32_timer_cnt *const priv = counter->priv; + int err; + u32 cr1; + bool enable; + + err = kstrtobool(buf, &enable); + if (err) + return err; + + if (enable) { + regmap_read(priv->regmap, TIM_CR1, &cr1); + if (!(cr1 & TIM_CR1_CEN)) + clk_enable(priv->clk); + + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, + TIM_CR1_CEN); + } else { + regmap_read(priv->regmap, TIM_CR1, &cr1); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + if (cr1 & TIM_CR1_CEN) + clk_disable(priv->clk); + } + + return len; +} + +static const struct counter_count_ext stm32_count_ext[] = { + { + .name = "direction", + .read = stm32_count_direction_read, + }, + { + .name = "enable", + .read = stm32_count_enable_read, + .write = stm32_count_enable_write + }, + { + .name = "ceiling", + .read = stm32_count_ceiling_read, + .write = stm32_count_ceiling_write + }, +}; + +enum stm32_synapse_action { + STM32_SYNAPSE_ACTION_NONE, + STM32_SYNAPSE_ACTION_BOTH_EDGES +}; + +static enum synapse_action stm32_synapse_actions[] = { + [STM32_SYNAPSE_ACTION_NONE] = SYNAPSE_ACTION_NONE, + [STM32_SYNAPSE_ACTION_BOTH_EDGES] = SYNAPSE_ACTION_BOTH_EDGES +}; + +static int stm32_action_get(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + size_t *action) +{ + size_t function; + int err; + + /* Default action mode (e.g. STM32_COUNT_SLAVE_MODE_DISABLED) */ + *action = STM32_SYNAPSE_ACTION_NONE; + + err = stm32_count_function_get(counter, count, &function); + if (err) + return 0; + + switch (function) { + case STM32_COUNT_ENCODER_MODE_1: + /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ + if (synapse->signal->id == count->synapses[0].signal->id) + *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; + break; + case STM32_COUNT_ENCODER_MODE_2: + /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ + if (synapse->signal->id == count->synapses[1].signal->id) + *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; + break; + case STM32_COUNT_ENCODER_MODE_3: + /* counts up/down on both TI1FP1 and TI2FP2 edges */ + *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; + break; + } + + return 0; +} + +static const struct counter_ops stm32_timer_cnt_ops = { + .count_read = stm32_count_read, + .count_write = stm32_count_write, + .function_get = stm32_count_function_get, + .function_set = stm32_count_function_set, + .action_get = stm32_action_get, +}; + +static struct counter_signal stm32_signals[] = { + { + .id = 0, + .name = "Channel 1 Quadrature A" + }, + { + .id = 1, + .name = "Channel 1 Quadrature B" + } +}; + +static struct counter_synapse stm32_count_synapses[] = { + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[0] + }, + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[1] + } +}; + +static struct counter_count stm32_counts = { + .id = 0, + .name = "Channel 1 Count", + .functions_list = stm32_count_functions, + .num_functions = ARRAY_SIZE(stm32_count_functions), + .synapses = stm32_count_synapses, + .num_synapses = ARRAY_SIZE(stm32_count_synapses), + .ext = stm32_count_ext, + .num_ext = ARRAY_SIZE(stm32_count_ext) +}; + +static int stm32_timer_cnt_probe(struct platform_device *pdev) +{ + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); + struct device *dev = &pdev->dev; + struct stm32_timer_cnt *priv; + + if (IS_ERR_OR_NULL(ddata)) + return -EINVAL; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->ceiling = ddata->max_arr; + + priv->counter.name = dev_name(dev); + priv->counter.parent = dev; + priv->counter.ops = &stm32_timer_cnt_ops; + priv->counter.counts = &stm32_counts; + priv->counter.num_counts = 1; + priv->counter.signals = stm32_signals; + priv->counter.num_signals = ARRAY_SIZE(stm32_signals); + priv->counter.priv = priv; + + /* Register Counter device */ + return devm_counter_register(dev, &priv->counter); +} + +static const struct of_device_id stm32_timer_cnt_of_match[] = { + { .compatible = "st,stm32-timer-counter", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match); + +static struct platform_driver stm32_timer_cnt_driver = { + .probe = stm32_timer_cnt_probe, + .driver = { + .name = "stm32-timer-counter", + .of_match_table = stm32_timer_cnt_of_match, + }, +}; +module_platform_driver(stm32_timer_cnt_driver); + +MODULE_AUTHOR("Benjamin Gaignard "); +MODULE_ALIAS("platform:stm32-timer-counter"); +MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver"); +MODULE_LICENSE("GPL v2");