From patchwork Thu Mar 15 15:52:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 10284905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A66260386 for ; Thu, 15 Mar 2018 15:53:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B32B28994 for ; Thu, 15 Mar 2018 15:53:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5FC872894E; Thu, 15 Mar 2018 15:53:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5CEF2869B for ; Thu, 15 Mar 2018 15:53:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932498AbeCOPw7 (ORCPT ); Thu, 15 Mar 2018 11:52:59 -0400 Received: from mail-yw0-f196.google.com ([209.85.161.196]:44084 "EHLO mail-yw0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932404AbeCOPw5 (ORCPT ); Thu, 15 Mar 2018 11:52:57 -0400 Received: by mail-yw0-f196.google.com with SMTP id x197so4899020ywg.11; Thu, 15 Mar 2018 08:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wkU5ZyNLgeRbt2NLKzHaXA7AeRJLDE8g1xRckDbikVk=; b=Q2asE4q0toH+tWdJ4iQQUeO77hHXXSHw+xWeB/hdVLX4wbiLp7kTfispObQtY+iOYf QCpdv5NpaB75Ox8aR6qtqBVTtMrqKPk/k629vqFEdDsnlYu6u+Zwvefashf0oG/Kq69F kO0F3/6ip7E6enw8NKI8lx8gHxPQMpRjxKKZD/rQV56Jb12ALhZR5Ev3lCVi3qCn9sx9 bHIqdScqpw3pYuvyZyvc7HRMV56ZWmtIigESRGS21O3NSvwc8HPAA65Vc6G6tOSMx9BM NdhHSSB3hr+vOINNdDMicTo+VeoqPsorYCakZ53MIo9lCzoXlM4n0IsvHWANr2diA0qP 0+9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wkU5ZyNLgeRbt2NLKzHaXA7AeRJLDE8g1xRckDbikVk=; b=Yfu63R0VAulmed2y0Y1LjP8ez4lxr1ZFSSQQ6dchdgZhi4EG9sXm3Yng0WSIGUtzo1 DUeHCJZbLSriQgEUxCUJz9jHqZDpv4SA6ZrB7uVqyigCGbVvMbE+pYOmdA8h/Hm2i5ER 9IPmhIHjfZJK+j6RSE8J3ymliWVTDuFD29uu6qyGxl6P/hfyez0nx+qEFTerCnwtgsm+ sHMSVMwV8/KDFrYepapNcOnDfYa8dgSklH6i+Kdz4A0NWws/oYqvRFQRNQsFVTimLNFJ DxDnusN4ssuuze26BNF/HCh4F4YPLkL9TTbCP67FxevpNwdIjGcRovhu3a3eTDly8417 l9aA== X-Gm-Message-State: AElRT7EdThM/DiR442bKAXJbpKI9G3MEq6rz0tNAWwSOWmVcBzD+ROe0 YZGP6pVPuuCTsRc4HE1m8ahd9A== X-Google-Smtp-Source: AG47ELvYNPT4UOPN+grBlzDFk7vepCxzXVJvSg+kSnrmMg+g+RFdyikiKTHcUmkxy0GR3bHhU3j/mQ== X-Received: by 2002:a25:80d1:: with SMTP id c17-v6mr6160527ybm.327.1521129176219; Thu, 15 Mar 2018 08:52:56 -0700 (PDT) Received: from localhost ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id p204sm2020833ywg.71.2018.03.15.08.52.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Mar 2018 08:52:55 -0700 (PDT) From: William Breathitt Gray To: linus.walleij@linaro.org Cc: andy.shevchenko@gmail.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, William Breathitt Gray Subject: [PATCH v2 4/8] gpio: pcie-idio-24: Implement get_multiple/set_multiple callbacks Date: Thu, 15 Mar 2018 11:52:44 -0400 Message-Id: <41c682a781e20b2db55491d36d600d56bb6b5c66.1521128287.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: References: Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ACCES I/O PCIe-IDIO-24 series of devices provides 24 optically-isolated digital I/O accessed via six 8-bit ports. Since eight input lines are acquired on a single port input read -- and similarly eight output lines are set on a single port output write -- the PCIe-IDIO-24 GPIO driver may improve multiple I/O reads/writes by utilizing a get_multiple/set_multiple callbacks. This patch implements the idio_24_gpio_get_multiple function which serves as the respective get_multiple callback, and implements the idio_24_gpio_set_multiple function which serves as the respective set_multiple callback. Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-pcie-idio-24.c | 118 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c index f666e2e69074..8d2f4745a13c 100644 --- a/drivers/gpio/gpio-pcie-idio-24.c +++ b/drivers/gpio/gpio-pcie-idio-24.c @@ -15,6 +15,7 @@ * This driver supports the following ACCES devices: PCIe-IDIO-24, * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12. */ +#include #include #include #include @@ -193,6 +194,61 @@ static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask); } +static int idio_24_gpio_get_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip); + size_t i; + const unsigned int gpio_reg_size = 8; + unsigned int bits_offset; + size_t word_index; + unsigned int word_offset; + unsigned long mask_word; + const unsigned long port_mask = GENMASK(gpio_reg_size, 0); + unsigned long port_state; + const u8 __iomem ports[] = { + idio24gpio->reg->out0_7, idio24gpio->reg->out8_15, + idio24gpio->reg->out16_23, idio24gpio->reg->in0_7, + idio24gpio->reg->in8_15, idio24gpio->reg->in16_23 + }; + const unsigned long out_mode_mask = BIT(1); + + /* clear bits array to a clean slate */ + bitmap_zero(bits, chip->ngpio); + + /* get bits are evaluated a gpio port register at a time */ + for (i = 0; i < ARRAY_SIZE(ports); i++) { + /* gpio offset in bits array */ + bits_offset = i * gpio_reg_size; + + /* word index for bits array */ + word_index = BIT_WORD(bits_offset); + + /* gpio offset within current word of bits array */ + word_offset = bits_offset % BITS_PER_LONG; + + /* mask of get bits for current gpio within current word */ + word_mask = mask[word_index] & (port_mask << word_offset); + if (!word_mask) { + /* no get bits in this port so skip to next one */ + continue; + } + + /* read bits from current gpio port (port 6 is TTL GPIO) */ + if (i < 6) + port_state = ioread8(ports + i); + else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) + port_state = ioread8(&idio24gpio->reg->ttl_out0_7); + else + port_state = ioread8(&idio24gpio->reg->ttl_in0_7); + + /* store acquired bits at respective bits array offset */ + bits[word_index] |= port_state << word_offset; + } + + return 0; +} + static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { @@ -234,6 +290,66 @@ static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset, raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); } +static void idio_24_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip); + size_t i; + unsigned long bits_offset; + unsigned long gpio_mask; + const unsigned int gpio_reg_size = 8; + const unsigned long port_mask = GENMASK(gpio_reg_size, 0); + unsigned long gpio_mask; + unsigned long flags; + unsigned int out_state; + const u8 __iomem ports[] = { + idio24gpio->reg->out0_7, idio24gpio->reg->out8_15, + idio24gpio->reg->out16_23 + }; + const unsigned long out_mode_mask = BIT(1); + const unsigned int ttl_offset = 48; + const size_t ttl_i = BIT_WORD(ttl_offset); + const unsigned int word_offset = ttl_offset % BITS_PER_LONG; + const unsigned long ttl_mask = (mask[ttl_i] >> word_offset) & port_mask; + const unsigned long ttl_bits = (bits[ttl_i] >> word_offset) & ttl_mask; + + /* set bits are processed a gpio port register at a time */ + for (i = 0; i < ARRAY_SIZE(ports); i++) { + /* gpio offset in bits array */ + bits_offset = i * gpio_reg_size; + + /* check if any set bits for current port */ + gpio_mask = (*mask >> bits_offset) & port_mask; + if (!gpio_mask) { + /* no set bits for this port so move on to next port */ + continue; + } + + raw_spin_lock_irqsave(&idio24gpio->lock, flags); + + /* process output lines */ + out_state = ioread8(ports + i) & ~gpio_mask; + out_state |= (*bits >> bits_offset) & gpio_mask; + iowrite8(out_state, ports + i); + + raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); + } + + /* check if setting TTL lines and if they are in output mode */ + if (!ttl_mask || !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask)) + return; + + /* handle TTL output */ + raw_spin_lock_irqsave(&idio24gpio->lock, flags); + + /* process output lines */ + out_state = ioread8(&idio24gpio->reg->ttl_out0_7) & ~ttl_mask; + out_state |= ttl_bits; + iowrite8(out_state, &idio24gpio->reg->ttl_out0_7); + + raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); +} + static void idio_24_irq_ack(struct irq_data *data) { } @@ -397,7 +513,9 @@ static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id) idio24gpio->chip.direction_input = idio_24_gpio_direction_input; idio24gpio->chip.direction_output = idio_24_gpio_direction_output; idio24gpio->chip.get = idio_24_gpio_get; + idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple; idio24gpio->chip.set = idio_24_gpio_set; + idio24gpio->chip.set = idio_24_gpio_set_multiple; raw_spin_lock_init(&idio24gpio->lock);