From patchwork Fri Dec 3 15:05:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sundar Iyer X-Patchwork-Id: 378291 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB3F8Rvm009958 for ; Fri, 3 Dec 2010 15:08:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750965Ab0LCPH1 (ORCPT ); Fri, 3 Dec 2010 10:07:27 -0500 Received: from eu1sys200aog110.obsmtp.com ([207.126.144.129]:54200 "EHLO eu1sys200aog110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750837Ab0LCPHW (ORCPT ); Fri, 3 Dec 2010 10:07:22 -0500 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob110.postini.com ([207.126.147.11]) with SMTP ID DSNKTPkHlWH3+5tV7clgdO9wwjcQEhd/uYSU@postini.com; Fri, 03 Dec 2010 15:07:20 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 600DC9A; Fri, 3 Dec 2010 15:06:58 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 106F6E68; Fri, 3 Dec 2010 15:06:58 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 3FDF424C2C0; Fri, 3 Dec 2010 16:06:50 +0100 (CET) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.2.254.0; Fri, 3 Dec 2010 16:06:57 +0100 From: Sundar Iyer To: , , , Cc: , , Sundar Iyer Subject: [PATCH 18/20] mach-ux500: explicit enable MTU TCR in the kernel Date: Fri, 3 Dec 2010 20:35:51 +0530 Message-ID: <1291388753-14662-19-git-send-email-sundar.iyer@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1291388753-14662-1-git-send-email-sundar.iyer@stericsson.com> References: <1291388753-14662-1-git-send-email-sundar.iyer@stericsson.com> MIME-Version: 1.0 Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 03 Dec 2010 15:08:29 +0000 (UTC) diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 531de5c..6657b05 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -132,7 +132,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) { void __iomem *addr = __io_address(UX500_PRCMU_BASE) + PRCM_TCR; - u32 tcr = readl(addr); + u32 tcr; int mtu = (int) clk->data; /* * One of these is selected eventually @@ -143,6 +143,14 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) unsigned long mturate; unsigned long retclk; + /* + * On a startup, always conifgure the TCR to the doze mode; + * bootloaders do it for us. Do this in the kernel too. + */ + writel(PRCM_TCR_DOZE_MODE, addr); + + tcr = readl(addr); + /* Get the rate from the parent as a default */ if (clk->parent_periph) mturate = clk_get_rate(clk->parent_periph); @@ -152,45 +160,6 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) /* We need to be connected SOMEWHERE */ BUG(); - /* - * Are we in doze mode? - * In this mode the parent peripheral or the fixed 32768 Hz - * clock is fed into the block. - */ - if (!(tcr & PRCM_TCR_DOZE_MODE)) { - /* - * Here we're using the clock input from the APE ULP - * clock domain. But first: are the timers stopped? - */ - if (tcr & PRCM_TCR_STOPPED) { - clk32k = 0; - mturate = 0; - } else { - /* Else default mode: 0 and 2.4 MHz */ - clk32k = 0; - if (cpu_is_u5500()) - /* DB5500 divides by 8 */ - mturate /= 8; - else if (cpu_is_u8500ed()) { - /* - * This clocking setting must not be used - * in the ED chip, it is simply not - * connected anywhere! - */ - mturate = 0; - BUG(); - } else - /* - * In this mode the ulp38m4 clock is divided - * by a factor 16, on the DB8500 typically - * 38400000 / 16 ~ 2.4 MHz. - * TODO: Replace the constant with a reference - * to the ULP source once this is modeled. - */ - mturate = 38400000 / 16; - } - } - /* Return the clock selected for this MTU */ if (tcr & (1 << mtu)) retclk = clk32k;