| Message ID | 1420511727-8242-3-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 06, 2015 at 10:35:12AM +0800, Chen-Yu Tsai wrote: > The cpu clock on sunxi machines is just a mux clock, which is normally > fed by the main PLL, but can be muxed to the main or low power oscillator. > > Make the mux clock propagate rate changes to its parent, so we can > change the clock rate of the PLL, and thus actually implement rate > changing on the cpu clock. > > This patch also removes the no reparenting limit. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Maxime
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index d8f17bbcb8e3..df18a2af33ad 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -778,7 +778,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); clk = clk_register_mux(NULL, clk_name, parents, i, - CLK_SET_RATE_NO_REPARENT, reg, + CLK_SET_RATE_PARENT, reg, data->shift, SUNXI_MUX_GATE_WIDTH, 0, &clk_lock);
The cpu clock on sunxi machines is just a mux clock, which is normally fed by the main PLL, but can be muxed to the main or low power oscillator. Make the mux clock propagate rate changes to its parent, so we can change the clock rate of the PLL, and thus actually implement rate changing on the cpu clock. This patch also removes the no reparenting limit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi/clk-sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)