From patchwork Tue Mar 21 15:36:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 9637395 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 525FA60327 for ; Tue, 21 Mar 2017 19:02:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 426272830A for ; Tue, 21 Mar 2017 19:02:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3680428418; Tue, 21 Mar 2017 19:02:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C88DE2830A for ; Tue, 21 Mar 2017 19:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758052AbdCUPgk (ORCPT ); Tue, 21 Mar 2017 11:36:40 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60414 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757931AbdCUPgh (ORCPT ); Tue, 21 Mar 2017 11:36:37 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 341E620B76; Tue, 21 Mar 2017 16:36:35 +0100 (CET) Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id C4EB3207CC; Tue, 21 Mar 2017 16:36:34 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 02/11] ARM: sun8i: a33: add all operating points Date: Tue, 21 Mar 2017 16:36:02 +0100 Message-Id: <20170321153611.16228-3-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds almost all operating points allowed for the A33 as defined by fex files available at: https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33 There are more possible frequencies in this patch than there are in the fex files because the fex files only give an interval of possible frequencies for a given voltage. All supported frequencies are defined in the original driver code in Allwinner vendor tree. There are two missing frequencies though: 1104MHz and 1200MHz which require the CPU to have 1.32V supplied, which is higher than the default voltage. Without all A33 boards defining the CPU regulator, we cannot have these two frequencies as it would cause the CPU to try to run a higher frequency without "overvolting" which is very likely to crash the CPU. Therefore, these two frequencies must be enabled on a per-board basis. Signed-off-by: Quentin Schulz Acked-by: Chen-Yu Tsai --- v2: - updated commit log, - removed 1.1GHz as it requires overvolting the CPU which need the CPU regulator to be set which is set on a per-board basis, arch/arm/boot/dts/sun8i-a33.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 39b2d78..b1cdff66 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -49,18 +49,72 @@ compatible = "operating-points-v2"; opp-shared; + opp@120000000 { + opp-hz = /bits/ 64 <120000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000>;