From patchwork Fri Nov 24 09:30:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 10073861 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 305CA60375 for ; Fri, 24 Nov 2017 09:31:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22F8A2A374 for ; Fri, 24 Nov 2017 09:31:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17A1B2A373; Fri, 24 Nov 2017 09:31:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9BB3B2A31A for ; Fri, 24 Nov 2017 09:30:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752955AbdKXJa6 (ORCPT ); Fri, 24 Nov 2017 04:30:58 -0500 Received: from mail-lf0-f67.google.com ([209.85.215.67]:43072 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752897AbdKXJa5 (ORCPT ); Fri, 24 Nov 2017 04:30:57 -0500 Received: by mail-lf0-f67.google.com with SMTP id 73so24709412lfu.10 for ; Fri, 24 Nov 2017 01:30:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FfCbL7POz2zTVSA27EZCFb4JYkm59xgZeWdYnwsfK6I=; b=NM80WJlTMnTFTzwL/a64VfAqTDuQ0YCQlvTQSrnxhgW0zWUb4AeelvO8Gl4wGNEum4 o+3XDRyF5IdWAJZVY+EfPU3HOayyDYv1kC82cOKHkn9S++oqmHaMVIbrYj93Ll8in9L9 Ulv8CnAPtaCP5batWbT+lPunCGg9Je4aIYDew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FfCbL7POz2zTVSA27EZCFb4JYkm59xgZeWdYnwsfK6I=; b=N8oGCX54VHJpf3FgMMXfHaUYg/PtUt89I39oUrtNgoa13tKnEZ3MlfJvJnhCbV3LKJ BNl0DAqrK2T9Z6OCG0xdqidzcVBudFuQA1aLDcCKCNWI0ScNBS8S5zqCuGJgKrQZJwbH n7QsKNMZZExgyj5MyVslBy/nFc45CNf42SjU3uJIolBbqvYx4XgR167C+mhw7/2GVWFH eZ6XCUDHUCfrPbRR1Fp8+9H75+i/IiCjnOe0FcNRXDMQL8WO9I9E6c8bU/bWEV29q0Pg tmh2CBsUPBBhL8vafuBEFnpyY/I/IQVs2LU5NnMW8kx8wQaG0Ht1To7ygQ/D9D0+FNEM /yBg== X-Gm-Message-State: AJaThX4r/9JMIr/SXTKYDam9sptjTCNGxbZUc1Ui4U31mhEE21KlKPrD 8Dhcf2UzB+YezmDiAaTUkIp55kCiLzI= X-Google-Smtp-Source: AGs4zMYey4JnLOhBjXr5kVBTZgFGK+baPnEfU2i/0nMqWeD8+scXG3LYUlWd/If5t2GByp2tY4B60A== X-Received: by 10.46.9.14 with SMTP id 14mr7460706ljj.175.1511515856013; Fri, 24 Nov 2017 01:30:56 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id 19sm4476608ljx.58.2017.11.24.01.30.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 24 Nov 2017 01:30:55 -0800 (PST) From: Linus Walleij To: Dmitry Torokhov , linux-input@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 4/5] ARM: imx: Give all GPIO chips a unique name Date: Fri, 24 Nov 2017 10:30:44 +0100 Message-Id: <20171124093045.5961-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171124093045.5961-1-linus.walleij@linaro.org> References: <20171124093045.5961-1-linus.walleij@linaro.org> Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The name/label of the GPIO chips is used in GPIO lookup tables so these need to be unique per chip. Suffix each GPIO chip with an instance number so these lookups will work as expected. Signed-off-by: Linus Walleij --- arch/arm/mach-imx/mm-imx21.c | 12 ++++++------ arch/arm/mach-imx/mm-imx27.c | 12 ++++++------ arch/arm/mach-imx/mm-imx3.c | 12 ++++++------ 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 2e91ab2ca378..9e7ec6f17d01 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -84,12 +84,12 @@ void __init imx21_soc_init(void) mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); mxc_device_init(); - mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-0", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-1", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-2", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-3", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-4", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-5", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); pinctrl_provide_dummies(); imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 862b9b7762c7..e2eb5dec659e 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -85,12 +85,12 @@ void __init imx27_soc_init(void) mxc_device_init(); /* i.mx27 has the i.mx21 type gpio */ - mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-0", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-1", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-2", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-3", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-4", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio-5", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); pinctrl_provide_dummies(); imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 7638a35b3b36..9568300f7554 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -188,9 +188,9 @@ void __init imx31_soc_init(void) mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); mxc_device_init(); - mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); + mxc_register_gpio("imx31-gpio-0", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); + mxc_register_gpio("imx31-gpio-1", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); + mxc_register_gpio("imx31-gpio-2", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); pinctrl_provide_dummies(); @@ -298,9 +298,9 @@ void __init imx35_soc_init(void) mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); mxc_device_init(); - mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); - mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); - mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); + mxc_register_gpio("imx35-gpio-0", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); + mxc_register_gpio("imx35-gpio-1", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); + mxc_register_gpio("imx35-gpio-2", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); pinctrl_provide_dummies(); if (to_version == 1) {