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Tue, 12 Jul 2022 18:19:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT050.mail.protection.outlook.com (10.13.173.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 18:19:28 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 13:19:26 -0500 From: Basavaraj Natikar To: , , CC: Basavaraj Natikar Subject: [PATCH 10/11] HID: amd_sfh: Move interrupt handling to common interface Date: Tue, 12 Jul 2022 23:48:35 +0530 Message-ID: <20220712181836.3488343-11-Basavaraj.Natikar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712181836.3488343-1-Basavaraj.Natikar@amd.com> References: <20220712181836.3488343-1-Basavaraj.Natikar@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0f7e9804-9d4c-4f18-db9b-08da64330f01 X-MS-TrafficTypeDiagnostic: MN0PR12MB5835:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 18:19:28.3298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f7e9804-9d4c-4f18-db9b-08da64330f01 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5835 Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org Interrupt handling can be used in multiple files to support all AMD SOCs. Hence move interrupt handling to common interface. Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_client.c | 6 ++---- drivers/hid/amd-sfh-hid/amd_sfh_common.h | 4 ++++ drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 8 ++++---- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_client.c b/drivers/hid/amd-sfh-hid/amd_sfh_client.c index 8e686081c8fc..f95e623040f3 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_client.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_client.c @@ -178,8 +178,7 @@ static void amd_sfh_resume(struct amd_mp2_dev *mp2) } schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP)); - if (mp2->mp2_ops->clear_intr) - mp2->mp2_ops->clear_intr(mp2); + amd_sfh_clear_intr(mp2); } static void amd_sfh_suspend(struct amd_mp2_dev *mp2) @@ -202,8 +201,7 @@ static void amd_sfh_suspend(struct amd_mp2_dev *mp2) } cancel_delayed_work_sync(&cl_data->work_buffer); - if (mp2->mp2_ops->clear_intr) - mp2->mp2_ops->clear_intr(mp2); + amd_sfh_clear_intr(mp2); } int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_common.h b/drivers/hid/amd-sfh-hid/amd_sfh_common.h index b3dd758ecca4..1efb72ec116f 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_common.h +++ b/drivers/hid/amd-sfh-hid/amd_sfh_common.h @@ -66,4 +66,8 @@ struct amd_mp2_ops { void amd_sfh_work(struct work_struct *work); void amd_sfh_work_buffer(struct work_struct *work); +void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata); +int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata); +void amd_sfh_clear_intr(struct amd_mp2_dev *privdata); +int amd_sfh_irq_init(struct amd_mp2_dev *privdata); #endif diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index c9a9ac11f124..1425b57f3580 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -92,7 +92,7 @@ static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata) writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); } -static void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata) +void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata) { if (readl(privdata->mmio + AMD_P2C_MSG(4))) { writel(0, privdata->mmio + AMD_P2C_MSG(4)); @@ -100,7 +100,7 @@ static void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata) } } -static void amd_sfh_clear_intr(struct amd_mp2_dev *privdata) +void amd_sfh_clear_intr(struct amd_mp2_dev *privdata) { if (privdata->mp2_ops->clear_intr) privdata->mp2_ops->clear_intr(privdata); @@ -113,7 +113,7 @@ static irqreturn_t amd_sfh_irq_handler(int irq, void *data) return IRQ_HANDLED; } -static int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata) +int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata) { int rc; @@ -279,7 +279,7 @@ static void mp2_select_ops(struct amd_mp2_dev *privdata) } } -static int amd_sfh_irq_init(struct amd_mp2_dev *privdata) +int amd_sfh_irq_init(struct amd_mp2_dev *privdata) { if (privdata->mp2_ops->init_intr) return privdata->mp2_ops->init_intr(privdata);