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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A2.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7002.20 via Frontend Transport; Fri, 17 Nov 2023 08:11:55 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 02:11:51 -0600 From: Shyam Sundar S K To: , , , , , CC: , , , , "Shyam Sundar S K" Subject: [PATCH v5 14/17] platform/x86/amd/pmf: Add PMF-AMDGPU set interface Date: Fri, 17 Nov 2023 13:37:44 +0530 Message-ID: <20231117080747.3643990-15-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117080747.3643990-1-Shyam-sundar.S-k@amd.com> References: <20231117080747.3643990-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|DM4PR12MB5793:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e9479aa-0ce9-4380-d0e3-08dbe744dcf4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 08:11:55.3256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e9479aa-0ce9-4380-d0e3-08dbe744dcf4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5793 For the Smart PC Solution to fully work, it has to enact to the actions coming from TA. Add the initial code path for set interface to AMDGPU. Change amd_pmf_apply_policies() return type, so that it can return errors when the call to retrieve information from amdgpu fails. Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/pmf.h | 2 ++ drivers/platform/x86/amd/pmf/tee-if.c | 39 +++++++++++++++++++++++++-- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 525308519fa3..6e680637a631 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -78,6 +78,7 @@ #define PMF_POLICY_STT_SKINTEMP_APU 7 #define PMF_POLICY_STT_SKINTEMP_HS2 8 #define PMF_POLICY_SYSTEM_STATE 9 +#define PMF_POLICY_DISPLAY_BRIGHTNESS 12 #define PMF_POLICY_P3T 38 /* TA macros */ @@ -503,6 +504,7 @@ enum ta_pmf_error_type { }; struct pmf_action_table { + unsigned long display_brightness; enum system_state system_state; u32 spl; /* in mW */ u32 sppt; /* in mW */ diff --git a/drivers/platform/x86/amd/pmf/tee-if.c b/drivers/platform/x86/amd/pmf/tee-if.c index 82ee2b1c627f..94a2afd84b56 100644 --- a/drivers/platform/x86/amd/pmf/tee-if.c +++ b/drivers/platform/x86/amd/pmf/tee-if.c @@ -77,8 +77,10 @@ static int amd_pmf_update_uevents(struct amd_pmf_dev *dev, u16 event) return 0; } -static void amd_pmf_apply_policies(struct amd_pmf_dev *dev, struct ta_pmf_enact_result *out) +static int amd_pmf_apply_policies(struct amd_pmf_dev *dev, struct ta_pmf_enact_result *out) { + struct thermal_cooling_device *cdev = dev->gfx_data.cooling_dev; + unsigned long state; u32 val; int idx; @@ -154,8 +156,21 @@ static void amd_pmf_apply_policies(struct amd_pmf_dev *dev, struct ta_pmf_enact_ dev_dbg(dev->dev, "update SYSTEM_STATE: %s\n", amd_pmf_uevent_as_str(val)); break; + + case PMF_POLICY_DISPLAY_BRIGHTNESS: + if (!dev->drm_dev) + return -ENODEV; + + cdev->ops->get_cur_state(cdev, &state); + if (state != val) { + cdev->ops->set_cur_state(cdev, val); + dev_dbg(dev->dev, "update DISPLAY_BRIGHTNESS: %u\n", val); + } + break; } } + + return 0; } static int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev) @@ -192,7 +207,9 @@ static int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev) amd_pmf_dump_ta_inputs(dev, in); dev_dbg(dev->dev, "action count:%u result:%x\n", out->actions_count, ta_sm->pmf_result); - amd_pmf_apply_policies(dev, out); + ret = amd_pmf_apply_policies(dev, out); + if (ret) + return ret; } return 0; @@ -423,6 +440,23 @@ static void amd_pmf_tee_deinit(struct amd_pmf_dev *dev) tee_client_close_context(dev->tee_ctx); } +static int amd_pmf_gpu_set_cur_state(struct thermal_cooling_device *cooling_dev, + unsigned long state) +{ + struct backlight_device *bd; + + if (acpi_video_get_backlight_type() != acpi_backlight_native) + return -ENODEV; + + bd = backlight_device_get_by_type(BACKLIGHT_RAW); + if (!bd) + return -ENODEV; + + backlight_device_set_brightness(bd, state); + + return 0; +} + static int amd_pmf_gpu_get_cur_state(struct thermal_cooling_device *cooling_dev, unsigned long *state) { @@ -463,6 +497,7 @@ static int amd_pmf_gpu_get_max_state(struct thermal_cooling_device *cooling_dev, static const struct thermal_cooling_device_ops bd_cooling_ops = { .get_max_state = amd_pmf_gpu_get_max_state, .get_cur_state = amd_pmf_gpu_get_cur_state, + .set_cur_state = amd_pmf_gpu_set_cur_state, }; static int amd_pmf_get_gpu_handle(struct pci_dev *pdev, void *data)