@@ -45,6 +45,9 @@
#define NVIDIA_BOOST_MAX 25
#define NVIDIA_TEMP_MIN 75
#define NVIDIA_TEMP_MAX 87
+#define NVIDIA_POWER_MIN 0
+#define NVIDIA_POWER_MAX 70
+#define NVIDIA_POWER_DEFAULT 70
#define PPT_CPU_LIMIT_MIN 5
#define PPT_CPU_LIMIT_MAX 150
#define PPT_CPU_LIMIT_DEFAULT 80
@@ -77,6 +80,11 @@ struct rog_tunables {
u32 nv_temp_min;
u32 nv_temp_max;
u32 nv_temp_target;
+
+ u32 dgpu_tgp_default;
+ u32 dgpu_tgp_min;
+ u32 dgpu_tgp_max;
+ u32 dgpu_tgp;
};
static const struct class *fw_attr_class;
@@ -477,6 +485,12 @@ ATTR_GROUP_ROG_TUNABLE(nv_dynamic_boost, "nv_dynamic_boost", ASUS_WMI_DEVID_NV_D
ATTR_GROUP_ROG_TUNABLE(nv_temp_target, "nv_temp_target", ASUS_WMI_DEVID_NV_THERM_TARGET,
nv_temp_default, nv_boost_min, nv_temp_max, 1,
"Set the Nvidia max thermal limit");
+ATTR_GROUP_ROG_TUNABLE(dgpu_tgp, "dgpu_tgp", ASUS_WMI_DEVID_DGPU_SET_TGP, dgpu_tgp_default,
+ dgpu_tgp_min, dgpu_tgp_max, 1,
+ "Set the additional TGP on top of the base TGP");
+
+ATTR_GROUP_INT_VALUE_ONLY_RO(dgpu_base_tgp, "dgpu_base_tgp", ASUS_WMI_DEVID_DGPU_BASE_TGP,
+ "Read the base TGP value");
ATTR_GROUP_ENUM_INT_RO(charge_mode, "charge_mode", ASUS_WMI_DEVID_CHARGE_MODE, "0;1;2",
"Show the current mode of charging");
@@ -505,6 +519,8 @@ static const struct asus_attr_group armoury_attr_groups[] = {
{ &ppt_fppt_attr_group, ASUS_WMI_DEVID_PPT_FPPT },
{ &nv_dynamic_boost_attr_group, ASUS_WMI_DEVID_NV_DYN_BOOST },
{ &nv_temp_target_attr_group, ASUS_WMI_DEVID_NV_THERM_TARGET },
+ { &dgpu_base_tgp_attr_group, ASUS_WMI_DEVID_DGPU_BASE_TGP },
+ { &dgpu_tgp_attr_group, ASUS_WMI_DEVID_DGPU_SET_TGP },
{ &charge_mode_attr_group, ASUS_WMI_DEVID_CHARGE_MODE },
{ &boot_sound_attr_group, ASUS_WMI_DEVID_BOOT_SOUND },
@@ -673,6 +689,11 @@ static void init_rog_tunables(struct rog_tunables *rog)
rog->nv_temp_max = NVIDIA_TEMP_MIN;
rog->nv_temp_max = NVIDIA_TEMP_MAX;
rog->nv_temp_target = NVIDIA_TEMP_MIN;
+
+ rog->dgpu_tgp_default = NVIDIA_POWER_DEFAULT;
+ rog->dgpu_tgp_min = NVIDIA_POWER_MIN;
+ rog->dgpu_tgp_max = NVIDIA_POWER_MAX;
+ rog->dgpu_tgp = NVIDIA_POWER_MAX;
}
static int __init asus_fw_init(void)
@@ -89,6 +89,20 @@ static ssize_t enum_type_show(struct kobject *kobj, struct kobj_attribute *attr,
static struct kobj_attribute attr_##_attrname##_##_prop = \
__ASUS_ATTR_RO(_attrname, _prop)
+/* Requires current_value_show */
+#define __ATTR_GROUP_INT_VALUE_ONLY(_attrname, _fsname, _dispname) \
+ __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \
+ static struct kobj_attribute attr_##_attrname##_type = \
+ __ASUS_ATTR_RO_AS(type, int_type_show); \
+ static struct attribute *_attrname##_attrs[] = { \
+ &attr_##_attrname##_current_value.attr, \
+ &attr_##_attrname##_display_name.attr, \
+ &attr_##_attrname##_type.attr, NULL \
+ }; \
+ static const struct attribute_group _attrname##_attr_group = { \
+ .name = _fsname, .attrs = _attrname##_attrs \
+ }
+
/* Boolean style enumeration, base macro. Requires adding show/store */
#define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \
__ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \
@@ -106,6 +120,10 @@ static ssize_t enum_type_show(struct kobject *kobj, struct kobj_attribute *attr,
.name = _fsname, .attrs = _attrname##_attrs \
}
+#define ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \
+ __ATTR_CURRENT_INT_RO(_attrname, _wmi); \
+ __ATTR_GROUP_INT_VALUE_ONLY(_attrname, _fsname, _dispname)
+
#define ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \
__ATTR_CURRENT_INT_RO(_attrname, _wmi); \
__ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname)
@@ -137,6 +137,9 @@
/* dgpu on/off */
#define ASUS_WMI_DEVID_DGPU 0x00090020
+#define ASUS_WMI_DEVID_DGPU_BASE_TGP 0x00120099
+#define ASUS_WMI_DEVID_DGPU_SET_TGP 0x00120098
+
/* gpu mux switch, 0 = dGPU, 1 = Optimus */
#define ASUS_WMI_DEVID_GPU_MUX 0x00090016
#define ASUS_WMI_DEVID_GPU_MUX_VIVO 0x00090026