From patchwork Wed Mar 6 18:28:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 2227821 Return-Path: X-Original-To: patchwork-linux-kbuild@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 5E7CB3FC8A for ; Wed, 6 Mar 2013 18:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754221Ab3CFS2s (ORCPT ); Wed, 6 Mar 2013 13:28:48 -0500 Received: from avon.wwwdotorg.org ([70.85.31.133]:42821 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754194Ab3CFS2r (ORCPT ); Wed, 6 Mar 2013 13:28:47 -0500 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 4ECF8642E; Wed, 6 Mar 2013 11:32:55 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id D1549E461E; Wed, 6 Mar 2013 11:28:44 -0700 (MST) From: Stephen Warren To: Stephen Warren Cc: Grant Likely , Rob Herring , Michal Marek , Shawn Guo , linux-kbuild@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, Stephen Warren Subject: [PATCH V2 2/6] ARM: tegra: fix sort order of USB PHY nodes Date: Wed, 6 Mar 2013 11:28:33 -0700 Message-Id: <1362594517-22099-2-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362594517-22099-1-git-send-email-swarren@wwwdotorg.org> References: <1362594517-22099-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean Sender: linux-kbuild-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kbuild@vger.kernel.org From: Stephen Warren The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 50 ++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index ab9402a..7708975 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -438,31 +438,6 @@ #size-cells = <0>; }; - phy1: usb-phy@c5000400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000400 0x3c00>; - phy_type = "utmi"; - nvidia,has-legacy-mode; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - - phy2: usb-phy@c5004400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004400 0x3c00>; - phy_type = "ulpi"; - clocks = <&tegra_car 94>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - - phy3: usb-phy@c5008400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008400 0x3C00>; - phy_type = "utmi"; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; @@ -475,6 +450,15 @@ status = "disabled"; }; + phy1: usb-phy@c5000400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5000400 0x3c00>; + phy_type = "utmi"; + nvidia,has-legacy-mode; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; @@ -485,6 +469,14 @@ status = "disabled"; }; + phy2: usb-phy@c5004400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004400 0x3c00>; + phy_type = "ulpi"; + clocks = <&tegra_car 94>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; @@ -495,6 +487,14 @@ status = "disabled"; }; + phy3: usb-phy@c5008400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5008400 0x3c00>; + phy_type = "utmi"; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>;