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Thu, 13 Oct 2022 21:41:28 -0700 Received: from xhdipdslab49.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 13 Oct 2022 23:41:20 -0500 From: Nipun Gupta To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Nipun Gupta Subject: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration for CDX bus Date: Fri, 14 Oct 2022 10:10:44 +0530 Message-ID: <20221014044049.2557085-4-nipun.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014044049.2557085-1-nipun.gupta@amd.com> References: <20220803122655.100254-1-nipun.gupta@amd.com> <20221014044049.2557085-1-nipun.gupta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT048:EE_|DM4PR12MB5136:EE_ X-MS-Office365-Filtering-Correlation-Id: 8193247b-d68a-4e67-49dd-08daad9e7082 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2022 04:42:02.8652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8193247b-d68a-4e67-49dd-08daad9e7082 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5136 Precedence: bulk List-ID: X-Mailing-List: linux-kbuild@vger.kernel.org With new CDX bus supported for AMD FPGA devices on ARM platform, the bus requires registration for the SMMU v3 driver. Signed-off-by: Nipun Gupta --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d32b02336411..8ec9f2baf12d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -29,6 +29,7 @@ #include #include +#include #include "arm-smmu-v3.h" #include "../../iommu-sva-lib.h" @@ -3690,16 +3691,27 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops) if (err) goto err_reset_pci_ops; } +#endif +#ifdef CONFIG_CDX_BUS + if (cdx_bus_type.iommu_ops != ops) { + err = bus_set_iommu(&cdx_bus_type, ops); + if (err) + goto err_reset_amba_ops; + } #endif if (platform_bus_type.iommu_ops != ops) { err = bus_set_iommu(&platform_bus_type, ops); if (err) - goto err_reset_amba_ops; + goto err_reset_cdx_ops; } return 0; -err_reset_amba_ops: +err_reset_cdx_ops: +#ifdef CONFIG_CDX_BUS + bus_set_iommu(&cdx_bus_type, NULL); +#endif +err_reset_amba_ops: __maybe_unused; #ifdef CONFIG_ARM_AMBA bus_set_iommu(&amba_bustype, NULL); #endif