From patchwork Sun Jun 25 09:56:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 13291859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 510C0C0015E for ; Sun, 25 Jun 2023 09:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231834AbjFYJ5K (ORCPT ); Sun, 25 Jun 2023 05:57:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231894AbjFYJ5E (ORCPT ); Sun, 25 Jun 2023 05:57:04 -0400 Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87D95122; Sun, 25 Jun 2023 02:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1687687021; bh=NOCcPZczdsomiPtC0nBfEgK1XfX0lPqE5Cxg6R5R4g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QyuMDzl+qZJTtAqG8alPlL2kyJVPBA+9zbR7KXmQXTev/Pq+GAjEsvF8qAvSxk9Vm JLuCmxj3iXT70ZB9kFoK9lYrgLQXHLb4X1IVlEEQgDMRP2aTPh0cpEnrAWqD1OQKFR zT2yyhhHtnCvzhNf3KIApx9QHKcX3oKV20uiwtK4= Received: from ld50.lan (unknown [101.88.25.181]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id EAE9D6015C; Sun, 25 Jun 2023 17:57:00 +0800 (CST) From: WANG Xuerui To: Huacai Chen Cc: WANG Rui , Xi Ruoyao , loongarch@lists.linux.dev, linux-kbuild@vger.kernel.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org, WANG Xuerui Subject: [PATCH v3 3/8] LoongArch: Prepare for assemblers with proper FCSR class support Date: Sun, 25 Jun 2023 17:56:39 +0800 Message-Id: <20230625095644.3156349-4-kernel@xen0n.name> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230625095644.3156349-1-kernel@xen0n.name> References: <20230625095644.3156349-1-kernel@xen0n.name> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kbuild@vger.kernel.org From: WANG Xuerui The GNU assembler (as of 2.40) mis-treats FCSR operands as GPRs, but the LLVM IAS does not. Probe for this and refer to FCSRs as "$fcsrNN" if support is present. Signed-off-by: WANG Xuerui --- arch/loongarch/Kconfig | 3 +++ arch/loongarch/include/asm/fpregdef.h | 7 +++++++ arch/loongarch/include/asm/loongarch.h | 9 ++++++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 743d87655742..ac3564935281 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -242,6 +242,9 @@ config SCHED_OMIT_FRAME_POINTER config AS_HAS_EXPLICIT_RELOCS def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x)) +config AS_HAS_FCSR_CLASS + def_bool $(as-instr,x:movfcsr2gr \$t0$(comma)\$fcsr0) + config CC_HAS_LSX_EXTENSION def_bool $(cc-option,-mlsx) diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h index b6be527831dd..3eb7ff9e1d8e 100644 --- a/arch/loongarch/include/asm/fpregdef.h +++ b/arch/loongarch/include/asm/fpregdef.h @@ -40,6 +40,12 @@ #define fs6 $f30 #define fs7 $f31 +#ifdef CONFIG_AS_HAS_FCSR_CLASS +#define fcsr0 $fcsr0 +#define fcsr1 $fcsr1 +#define fcsr2 $fcsr2 +#define fcsr3 $fcsr3 +#else /* * Current binutils expects *GPRs* at FCSR position for the FCSR * operation instructions, so define aliases for those used. @@ -48,5 +54,6 @@ #define fcsr1 $r1 #define fcsr2 $r2 #define fcsr3 $r3 +#endif #endif /* _ASM_FPREGDEF_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index ac83e60c60d1..ff4482fd8ad7 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -1445,11 +1445,18 @@ __BUILD_CSR_OP(tlbidx) #define EXCCODE_INT_START 64 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) -/* FPU register names */ +/* FPU Status Register Names */ +#ifdef CONFIG_AS_HAS_FCSR_CLASS +#define LOONGARCH_FCSR0 $fcsr0 +#define LOONGARCH_FCSR1 $fcsr1 +#define LOONGARCH_FCSR2 $fcsr2 +#define LOONGARCH_FCSR3 $fcsr3 +#else #define LOONGARCH_FCSR0 $r0 #define LOONGARCH_FCSR1 $r1 #define LOONGARCH_FCSR2 $r2 #define LOONGARCH_FCSR3 $r3 +#endif /* FPU Status Register Values */ #define FPU_CSR_RSVD 0xe0e0fce0