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[0/2] selftest/x86: AMX CPU state management tests

Message ID 20211026122523.AFB99C1F@davehans-spike.ostc.intel.com (mailing list archive)
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Series selftest/x86: AMX CPU state management tests | expand

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Dave Hansen Oct. 26, 2021, 12:25 p.m. UTC 
Intel Advanced Matrix Extensions (AMX) are a new set registers
and ISA.  They are conceptually similar to the earlier AVX and
SSE ISA.  But, the registers as a whole are *really* big: ~8k
verus 2k for AVX-512.

Those amply-sized registers present some potential problems with
task_struct and signal stack bloat.  To fix those issues, most of
the new AMX state is dynamically allocated with the help of a new
CPU feature.

This new selftest exercises the new dynamic allocation ABI and
also ensures that AMX state is properly context-switched.

Processors that support AMX (Sapphire Rapids) are not publicly
available.  The kernel support needed to run these tests is not
upstream.  This selftest was developed against this tree:

	https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/log/?h=x86/fpu

These tests were primarily written by Chang Bae.  He's busy
working on the real kernel support, so I stole these and cleaned
them up a bit.

Chang S. Bae (2):
      selftest/x86/amx: Test cases for the AMX state management
      selftest/x86/amx: Add context switch test

 tools/testing/selftests/x86/Makefile |   2 +-
 tools/testing/selftests/x86/amx.c    | 851 +++++++++++++++++++++++++++
 2 files changed, 852 insertions(+), 1 deletion(-)

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-kselftest@vger.kernel.org