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[v2,0/6] Extend pmu_counters_test to AMD CPUs

Message ID 20240918205319.3517569-1-coltonlewis@google.com (mailing list archive)
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Series Extend pmu_counters_test to AMD CPUs | expand

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Colton Lewis Sept. 18, 2024, 8:53 p.m. UTC 
Extend pmu_counters_test to AMD CPUs.

As the AMD PMU is quite different from Intel with different events and
feature sets, this series introduces a new code path to test it,
specifically focusing on the core counters including the
PerfCtrExtCore and PerfMonV2 features. Northbridge counters and cache
counters exist, but are not as important and can be deferred to a
later series.

The first patch is a bug fix that could be submitted separately.

The series has been tested on both Intel and AMD machines, but I have
not found an AMD machine old enough to lack PerfCtrExtCore. I have
made efforts that no part of the code has any dependency on its
presence.

I am aware of similar work in this direction done by Jinrong Liang
[1]. He told me he is not working on it currently and I am not
intruding by making my own submission.

[1] https://lore.kernel.org/kvm/20231121115457.76269-1-cloudliang@tencent.com/

v2:
* Test all combinations of VM setup rather than only the maximum
  allowed by hardware
* Add fixes tag to bug fix in patch 1
* Refine some names

v1:
https://lore.kernel.org/kvm/20240813164244.751597-1-coltonlewis@google.com/

Colton Lewis (6):
  KVM: x86: selftests: Fix typos in macro variable use
  KVM: x86: selftests: Define AMD PMU CPUID leaves
  KVM: x86: selftests: Set up AMD VM in pmu_counters_test
  KVM: x86: selftests: Test read/write core counters
  KVM: x86: selftests: Test core events
  KVM: x86: selftests: Test PerfMonV2

 .../selftests/kvm/include/x86_64/processor.h  |   7 +
 .../selftests/kvm/x86_64/pmu_counters_test.c  | 304 ++++++++++++++++--
 2 files changed, 277 insertions(+), 34 deletions(-)


base-commit: da3ea35007d0af457a0afc87e84fddaebc4e0b63
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2.46.0.662.g92d0881bb0-goog