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Fri, 24 Jan 2025 16:31:03 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 09/14] iommufd/selftest: Add IOMMU_TEST_OP_TRIGGER_VEVENT for vEVENTQ coverage Date: Fri, 24 Jan 2025 16:30:38 -0800 Message-ID: <0f5250dc0fd17234cce91d45a869c4f8dbace56e.1737754129.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|PH0PR12MB7815:EE_ X-MS-Office365-Filtering-Correlation-Id: d4159c95-de92-440a-bbea-08dd3cd794d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: ZGvYFnQf84j0XOtG7sAtIVK1POliIWyQi8W1fMM8vO60bJMmT2JRdBOg35QTwOljumsoJyQJxytGokQkgKI8UdKMCIi/AKRmFcPpuCKWNkHxgjjZ50SPR/RficXI5peaMlay+LjeTNRFg8HZzWd/P/Kd5HwR6xR3eZcTull29E3me8Vayh57J5PCAI2ebAMTGV2advNCLUtfCG1GiN+dCZUYEpQB695l4kHoiU0cUaIS+5z4V5AQcTAt2tSYlAaoX53hO6s9I+RCm3tPzvQFg7vVsqipHj3Y7+3TN87Sh2ZbmhuXG5oivq1ZZOsKuSSiKM690+N5wNsoZUvoSLHRmVOU9A3V7ScCxbZ+mhDnaIqYmd/7nW10RNakU+5YLZjJYXwOuqsD2KKgXclMZSB8UliTNIHkmjzDlsRGfZwKgw2hS54T0JocEtvwCLH9VYPXr18lxDrhxegbq/9UTq9pMNC8zefW0d+AQTNV9RU+ESd2dOaTlj6S7uU3a2beigHe6eviArg2otMEhaSNO9DxfvrPMBql4QTY+sYM+f4ctjAMKODguvEQJcUbRyJgQMTDCuLzMqSJfla3HZd14QGqMopkgbNAvo6sBeLoX7e2hkWvn5CV5E0tE3bf9pesanTT4Zcl+bj5ZjuzEMwfTXIAYh8mGmERdOCkDYBbvCRadMpAejdvfwnUGF5VbiYjz/dBM57sX1o2opK7vQ7ERPWeb3q18jqVWheGXgbiPM1Getn2cdcwN7Dur+RdyflwamdEzSJ/9+Riww5qKqBd2TC2pM9YGURHt6NzCYNPhzzLgP0+Du0x1waW1XjERtnryelcl7qApFb1mTaEwHSDXtthJxfCnjuITfQOLwJiwmdtroK8ZR74tYQrlkuS3E69DCAZ5APvdEcpxyjGKnsIEA5MXFlfY1UkEBzCJRaMlVIxa9zEA3WUxn0ipebNyV5TzeLzgAeR/m9q7qBYK2eUyb0BbPul4XFvH1yS1n/KNo+iP+oe4XiuKOEUSC3Jyv19F2/FLVB4dKa99zFa2DfuC6sRw3O8NlEQnaBNE+lY0tSzePYKa0zkodjrP6UU+FrbfUDud5abItQJ45YagEqna4HFbd5afy+hgvSQXWCzPouRW/DmjM1ck+J+qN2wuOJKu8axhddW7QuCqgtZIVmH0UhXVN+VrlHSE4P9Ie5vfXP9rCe5kjRHwQCEzoxBmYZtSLAdW7mALtmoYOU0ESvegzIScBaZx3haABf6DwmmRcNU21GLDDnFXBg4EwCuyBZA79Ap2PWVpFDTLzCGTSoAAVTk0ykCo1RjjYq9dbty8QVQ+q3QYLFHlsIBk+R8OIQ71oM6YPwF+x8+f03Uub2esxtrO9OxCUeZn3pafxQ+cTFKUH+oJBLwN2Qvd1+HIcviYitJ5+YyvxhjJba9dK4zT0WcbyFeRYGlVHGNuOhoM3ZZyBV1H6KChbSp8n0qaSLTm8/1UzChkYnSto9h1ThLozP1tgZUPQ3WTTx0kMjp/cxNApg= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2025 00:31:16.7183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4159c95-de92-440a-bbea-08dd3cd794d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7815 The handler will get vDEVICE object from the given mdev and convert it to its per-vIOMMU virtual ID to mimic a real IOMMU driver. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_test.h | 10 ++++++++++ drivers/iommu/iommufd/selftest.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h index a6b7a163f636..87e9165cea27 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -24,6 +24,7 @@ enum { IOMMU_TEST_OP_MD_CHECK_IOTLB, IOMMU_TEST_OP_TRIGGER_IOPF, IOMMU_TEST_OP_DEV_CHECK_CACHE, + IOMMU_TEST_OP_TRIGGER_VEVENT, }; enum { @@ -145,6 +146,9 @@ struct iommu_test_cmd { __u32 id; __u32 cache; } check_dev_cache; + struct { + __u32 dev_id; + } trigger_vevent; }; __u32 last; }; @@ -212,4 +216,10 @@ struct iommu_viommu_invalidate_selftest { __u32 cache_id; }; +#define IOMMU_VEVENTQ_TYPE_SELFTEST 0xbeefbeef + +struct iommu_viommu_event_selftest { + __u32 virt_id; +}; + #endif diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index d786561359c4..0ebaaf795676 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -1632,6 +1632,34 @@ static int iommufd_test_trigger_iopf(struct iommufd_ucmd *ucmd, return 0; } +static int iommufd_test_trigger_vevent(struct iommufd_ucmd *ucmd, + struct iommu_test_cmd *cmd) +{ + struct iommu_viommu_event_selftest test = {}; + struct iommufd_device *idev; + struct mock_dev *mdev; + int rc = -ENOENT; + + idev = iommufd_get_device(ucmd, cmd->trigger_vevent.dev_id); + if (IS_ERR(idev)) + return PTR_ERR(idev); + mdev = to_mock_dev(idev->dev); + + down_read(&mdev->viommu_rwsem); + if (!mdev->viommu || !mdev->vdev_id) + goto out_unlock; + + test.virt_id = mdev->vdev_id; + rc = iommufd_viommu_report_event(&mdev->viommu->core, + IOMMU_VEVENTQ_TYPE_SELFTEST, &test, + sizeof(test)); +out_unlock: + up_read(&mdev->viommu_rwsem); + iommufd_put_object(ucmd->ictx, &idev->obj); + + return rc; +} + void iommufd_selftest_destroy(struct iommufd_object *obj) { struct selftest_obj *sobj = to_selftest_obj(obj); @@ -1713,6 +1741,8 @@ int iommufd_test(struct iommufd_ucmd *ucmd) cmd->dirty.flags); case IOMMU_TEST_OP_TRIGGER_IOPF: return iommufd_test_trigger_iopf(ucmd, cmd); + case IOMMU_TEST_OP_TRIGGER_VEVENT: + return iommufd_test_trigger_vevent(ucmd, cmd); default: return -EOPNOTSUPP; }