From patchwork Mon Oct 18 19:08:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12567777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 425FEC433F5 for ; Mon, 18 Oct 2021 19:10:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25B296128B for ; Mon, 18 Oct 2021 19:10:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231890AbhJRTND (ORCPT ); Mon, 18 Oct 2021 15:13:03 -0400 Received: from mail.kernel.org ([198.145.29.99]:38220 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229924AbhJRTND (ORCPT ); Mon, 18 Oct 2021 15:13:03 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8A44B6128A; Mon, 18 Oct 2021 19:10:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634584252; bh=vmrnb4pZHUUx1LULEOYHjo+TlRUPJefDCczU3XrbKj4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uOKocOgAf+HDD4drB7nAa8KonBrtVZmCn2E1B2PP+8HyX6jibrRppX1u/YTNEvQIz 6OmIjvC7lQZTmyJONb9rHDeyaSZ0ERCmrxaSUpHUT8sZY6nHxIJRhEJ0eKjpOSWKgI BG3pMFsjA5EtATQxlqSLACVsy2i3xDNI1G/KxxByr2/GVgmkr3PKepE6y4ZV8bZHNh CtVAVnQuGnqwtVXJ5S0HU4vIsgZZ6dCDZmsWrml8ZK4WXFcNMAs9LTmovZT3oP8yZb /shJWV4K5DTwl5ZqVPFEaf1pAqPwspAWhkWWTWl0bzVa6KzkVVd5M+Bltcwl9yyIUr tz6vOhopP3wjw== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 17/42] arm64/sme: Define macros for manually encoding SME instructions Date: Mon, 18 Oct 2021 20:08:33 +0100 Message-Id: <20211018190858.2119209-18-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211018190858.2119209-1-broonie@kernel.org> References: <20211018190858.2119209-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2142; h=from:subject; bh=vmrnb4pZHUUx1LULEOYHjo+TlRUPJefDCczU3XrbKj4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBhbcY0sa4NV0tNF/cVSQTzhYx2Lrx0YXiiTS2B3EK8 94Z4JiGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYW3GNAAKCRAk1otyXVSH0MveB/ 9ayPkVSERtHrIlDC866sWID66Ms+71wSQ75c8jUcLweRimYnqojZIj6mh4M9FTt4f61oCwZxC7eqpj NJ0vzOlvOArAtF4SAxRRzD0S7LnCsSzi3WyPAlOK8jH2o0M7d75IJsc9KfaX0PwCQsRqyhpU/OraGW LezLGAIWeHl0wNHGSdrcdB567Sh/JlzcC2fOLkKKpjUQ2hO0SR0A5otzLcAlHChJMbMIT9CjYKEZwh 0gyySOq34qTVb+TeahDjKFtjkfU4+RLVT25e2BZcbcjI+OvQ+xUR0XMZfpUs1EYpu3fBjfMOxwOxhP Utxin1CWYluGwMVjt58dMLXEFgNgwe X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org As with SVE rather than impose ambitious toolchain requirements for SME we manually encode the few instructions which we require in order to perform the work the kernel needs to do. That is currently: - Vector store and load for the ZA array. - Zeroing of the whole ZA array. This does not include the SMSTART and SMSTOP instructions which are single instructions and only used from C code, a later patch will define them as inline assembly. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimdmacros.h | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h index b22538a6137e..bc45bb984c49 100644 --- a/arch/arm64/include/asm/fpsimdmacros.h +++ b/arch/arm64/include/asm/fpsimdmacros.h @@ -93,6 +93,12 @@ .endif .endm +.macro _sme_check_wv v + .if (\v) < 12 || (\v) > 15 + .error "Bad vector select register \v." + .endif +.endm + /* SVE instruction encodings for non-SVE-capable assemblers */ /* (pre binutils 2.28, all kernel capable clang versions support SVE) */ @@ -174,6 +180,44 @@ | (\np) .endm +/* SME instruction encodings for non-SME-capable assemblers */ + +/* + * STR (vector from ZA array): + * STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL] + */ +.macro _sme_str_zav nw, nxbase, offset=0 + _sme_check_wv \nw + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe1200000 \ + | (((\nw) & 3) << 13) \ + | ((\nxbase) << 5) \ + | ((\offset) & 7) +.endm + +/* + * LDR (vector to ZA array): + * LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL] + */ +.macro _sme_ldr_zav nw, nxbase, offset=0 + _sme_check_wv \nw + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe1000000 \ + | (((\nw) & 3) << 13) \ + | ((\nxbase) << 5) \ + | ((\offset) & 7) +.endm + +/* + * Zero the entire ZA array + * ZERO ZA + */ +.macro zero_za + .inst 0xc00800ff +.endm + .macro __for from:req, to:req .if (\from) == (\to) _for__body %\from