From patchwork Mon Nov 15 15:28:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12619791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4EBDC433FE for ; Mon, 15 Nov 2021 15:30:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 995E463212 for ; Mon, 15 Nov 2021 15:30:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236544AbhKOPct (ORCPT ); Mon, 15 Nov 2021 10:32:49 -0500 Received: from mail.kernel.org ([198.145.29.99]:52348 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236522AbhKOPcX (ORCPT ); Mon, 15 Nov 2021 10:32:23 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1BE8363212; Mon, 15 Nov 2021 15:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1636990168; bh=hGpG8Ecn+fUBYk7jzxhxs/HLYdIhbVwbCQFcqoaHYxE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ham/FVQXfw+uTMiG9uZ+CIYanf0x2o7QFRe1xBMo66MHc5Mjc0dNu6kTlDzVNVPJV oN4Ks/ZwdauGA+lBzxK72xZ1xRkI1RqX6RivxJourx3YaVSobwnGUMIhEHz41WZ31/ cruKAqrr8aU4t+WZwa1fDA1iGbGSOA6wOxZRJANeeviFg6QEiHZRC4zeVyuwV4Ib4Q smmiW88J2dIgfUiH1+QtVvwHh9nTMyNW1uVqYFlgDkOy3QWV1pHOo8afYlz66IXar4 FxP0wpV1KN9oAv+yPks4YKXx4cvRVCKtg8eApB1U1ECGh+9fG8ATbtVfCwjwzunUBQ e3WdxFg97RSeg== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v6 12/37] arm64/sme: Early CPU setup for SME Date: Mon, 15 Nov 2021 15:28:10 +0000 Message-Id: <20211115152835.3212149-13-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211115152835.3212149-1-broonie@kernel.org> References: <20211115152835.3212149-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2490; h=from:subject; bh=hGpG8Ecn+fUBYk7jzxhxs/HLYdIhbVwbCQFcqoaHYxE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBhknyOyLv2zpnBGtW8BWzvZn6mB1Qgl6PW4FK9CnpW RlSAmYuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYZJ8jgAKCRAk1otyXVSH0HVbB/ 9A1wxCWtC7lo0MKobdP6ympdpNqI64P3CSf7kPEQHbSJRE9POCGbzU0qgP3tqAP0C0PWAAMwWa16Te j9CDzOINaaLHnkFGDCs0PZFaIQIwnhA8UFGzm1rdfh48gj0xbWPisTVryj3Srer5mdK06+rHeX+ArA 1GECiyuBM7sJqyEI9czby5+nhawBXaCPrMxmNd8AscbONonqGtK124x2X93a0wvdF60uJtPX0nvIZB MLzDm/HARx4ErvxGe+Ufg7cSBvR+b6NSCXTcym0eVFwNdkySH7X3eKLEVyogiPacoIPvNQjSPK3Jq1 Hciei922v1LTb4upJOf01F+vECxwJC X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org SME requires similar setup to that for SVE: disable traps to EL2 and make sure that the maximum vector length is available to EL1, for SME we have two traps - one for SME itself and one for TPIDR2. In addition since we currently make no active use of priority control for SCMUs we map all SME priorities lower ELs may configure to 0, the architecture specified minimum priority, to ensure that nothing we manage is able to configure itself to consume excessive resources. This will need to be revisited should there be a need to manage SME priorities at runtime. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 45 ++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 3198acb2aad8..ea13041a2392 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -143,6 +143,50 @@ .Lskip_sve_\@: .endm +/* SME register access and priority mapping */ +.macro __init_el2_nvhe_sme + mrs x1, id_aa64pfr1_el1 + ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4 + cbz x1, .Lskip_sme_\@ + + bic x0, x0, #CPTR_EL2_TSM // Also disable SME traps + msr cptr_el2, x0 // Disable copro. traps to EL2 + isb + + mrs x1, sctlr_el2 + orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps + msr sctlr_el2, x1 + isb + + mov x1, #0 // SMCR controls + + mrs_s x2, SYS_ID_AA64SMFR0_EL1 + ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM? + cbz x2, .Lskip_sme_fa64_\@ + + orr x1, x1, SMCR_ELx_FA64_MASK +.Lskip_sme_fa64_\@: + + orr x1, x1, #SMCR_ELx_LEN_MASK // Enable full SME vector + msr_s SYS_SMCR_EL2, x1 // length for EL1. + + mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? + ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1 + cbz x1, .Lskip_sme_\@ + + msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal + + mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present? + ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4 + cbz x1, .Lskip_sme_\@ + + mrs_s x1, SYS_HCRX_EL2 + orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping + msr_s SYS_HCRX_EL2, x1 + +.Lskip_sme_\@: +.endm + /* Disable any fine grained traps */ .macro __init_el2_fgt mrs x1, id_aa64mmfr0_el1 @@ -196,6 +240,7 @@ __init_el2_nvhe_idregs __init_el2_nvhe_cptr __init_el2_nvhe_sve + __init_el2_nvhe_sme __init_el2_fgt __init_el2_nvhe_prepare_eret .endm