| Message ID | 20230109130605.2013555-2-eesposit@redhat.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 052c3b99cbc8d227f8cb8edf1519197808d1d653 |
| Headers | show |
| Series | xapic: make sure x2APIC -> xapic transition correctly | expand |
On Mon, 2023-01-09 at 08:06 -0500, Emanuele Giuseppe Esposito wrote: > If KVM_SET_MSR firstly enables and then disables x2APIC, make sure > APIC_ID is actually updated correctly, since bits and offset differ from > xAPIC and x2APIC. > > Currently this is not handled correctly, as kvm_set_apic_base() will > have msr_info->host_initiated, so switching from x2APIC to xAPIC won't > fail, but kvm_lapic_set_base() does not handle the case. > > Fixes: 8d860bbeedef ("kvm: vmx: Basic APIC virtualization controls have three settings") > Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> > --- > arch/x86/kvm/lapic.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 4efdb4a4d72c..df0a50099aa2 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2394,8 +2394,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) > } > } > > - if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) > - kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); > + if ((old_value ^ value) & X2APIC_ENABLE) { > + if (value & X2APIC_ENABLE) > + kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); > + else > + kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); > + } > > if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { > kvm_vcpu_update_apicv(vcpu); I don't think that this patch is 100% needed in a strict sense, but I don't object to it either. The switch between x2apic and xapic mode is not allowed by X86 spec, while vise versa is allowed and I think that the spec says that in this case APIC ID is restored to its default value. When QEMU does x2apic->xapic switch anyway to reset the vCPU, it should both upload the IA32_APIC_BASE and all of the apic registers via KVM_SET_LAPIC, and it looks like that is what Qemu does: static void kvm_apic_put(CPUState *cs, run_on_cpu_data data) { ... // this calls KVM_SET_MSRS with MSR_IA32_APICBASE, and APIC might be with wrong apic id after this kvm_put_apicbase(s->cpu, s->apicbase); // this just initializes the kapic with apic state to upload kvm_put_apic_state(s, &kapic); // and this uploads the apic state, including the APIC ID register ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); if (ret < 0) { fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(-ret)); abort(); } } SO between KVM_SET_MSRS and KVM_SET_LAPIC, apic id is indeed != vcpu_id, which might inhibit APICv/AVIC but after recent Sean's patch series, the inhibition is now reversible. In fact I think it won't hurt to make the APICV_INHIBIT_REASON_APIC_BASE_MODIFIED inhibition reversible as well. Best regards, Maxim Levitsky
On Mon, Jan 09, 2023, Maxim Levitsky wrote: > On Mon, 2023-01-09 at 08:06 -0500, Emanuele Giuseppe Esposito wrote: > > If KVM_SET_MSR firstly enables and then disables x2APIC, make sure > > APIC_ID is actually updated correctly, since bits and offset differ from > > xAPIC and x2APIC. > > > > Currently this is not handled correctly, as kvm_set_apic_base() will > > have msr_info->host_initiated, so switching from x2APIC to xAPIC won't > > fail, but kvm_lapic_set_base() does not handle the case. > > > > Fixes: 8d860bbeedef ("kvm: vmx: Basic APIC virtualization controls have three settings") > > Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> > > --- > > arch/x86/kvm/lapic.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > index 4efdb4a4d72c..df0a50099aa2 100644 > > --- a/arch/x86/kvm/lapic.c > > +++ b/arch/x86/kvm/lapic.c > > @@ -2394,8 +2394,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) > > } > > } > > > > - if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) > > - kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); > > + if ((old_value ^ value) & X2APIC_ENABLE) { > > + if (value & X2APIC_ENABLE) > > + kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); > > + else > > + kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); > > + } > > > > if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { > > kvm_vcpu_update_apicv(vcpu); > > > I don't think that this patch is 100% needed in a strict sense, but I don't > object to it either. I'd prefer not to go this route, I assume/suspect there's a diffferent underlying issue that is the real problem. > The switch between x2apic and xapic mode is not allowed by X86 spec, while > vise versa is allowed and I think that the spec says that in this case APIC > ID is restored to its default value. No, APIC ID is initialized on RESET, but AFAIK it's preserved for all other transitions. It's definitely preserved on INIT (doesn't touch the enable bit), and this snippet from the SDM more or less says the APIC ID is preserved when it's disabled in IA32_APIC_BASE. From the disabled state, the only valid x2APIC transition using IA32_APIC_BASE is to the xAPIC mode (EN= 1, EXTD = 0). Thus the only means to transition from x2APIC mode to xAPIC mode is a two-step process: - first transition from x2APIC mode to local APIC disabled mode (EN= 0, EXTD = 0), - followed by another transition from disabled mode to xAPIC mode (EN= 1, EXTD= 0). Consequently, all the APIC register states in the x2APIC, except for the x2APIC ID (32 bits), are not preserved across mode transitions. And for RESET vs. INIT A reset in this state places the x2APIC in xAPIC mode. All APIC registers (including the local APIC ID register) are initialized as described in Section 10.12.5.1. An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the local APIC ID register is preserved (all 32 bits). However, all the other APIC registers are initialized as a result of the INIT transition. Emanuele, what is the actual issue you are trying to fix? E.g. is APICv left inihibited after an emulated RESET? Something else? Stuffing APIC state from userspace should do the right thing after commit ef40757743b4 ("KVM: x86: fix APICv/x2AVIC disabled when vm reboot by itself") and this patch: https://lore.kernel.org/all/20230106011306.85230-33-seanjc@google.com
Am 09/01/2023 um 17:23 schrieb Sean Christopherson: > On Mon, Jan 09, 2023, Maxim Levitsky wrote: >> On Mon, 2023-01-09 at 08:06 -0500, Emanuele Giuseppe Esposito wrote: >>> If KVM_SET_MSR firstly enables and then disables x2APIC, make sure >>> APIC_ID is actually updated correctly, since bits and offset differ from >>> xAPIC and x2APIC. >>> >>> Currently this is not handled correctly, as kvm_set_apic_base() will >>> have msr_info->host_initiated, so switching from x2APIC to xAPIC won't >>> fail, but kvm_lapic_set_base() does not handle the case. >>> >>> Fixes: 8d860bbeedef ("kvm: vmx: Basic APIC virtualization controls have three settings") >>> Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> >>> --- >>> arch/x86/kvm/lapic.c | 8 ++++++-- >>> 1 file changed, 6 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c >>> index 4efdb4a4d72c..df0a50099aa2 100644 >>> --- a/arch/x86/kvm/lapic.c >>> +++ b/arch/x86/kvm/lapic.c >>> @@ -2394,8 +2394,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) >>> } >>> } >>> >>> - if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) >>> - kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); >>> + if ((old_value ^ value) & X2APIC_ENABLE) { >>> + if (value & X2APIC_ENABLE) >>> + kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); >>> + else >>> + kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); >>> + } >>> >>> if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { >>> kvm_vcpu_update_apicv(vcpu); >> >> >> I don't think that this patch is 100% needed in a strict sense, but I don't >> object to it either. > > I'd prefer not to go this route, I assume/suspect there's a diffferent underlying > issue that is the real problem. > >> The switch between x2apic and xapic mode is not allowed by X86 spec, while >> vise versa is allowed and I think that the spec says that in this case APIC >> ID is restored to its default value. > > No, APIC ID is initialized on RESET, but AFAIK it's preserved for all other > transitions. It's definitely preserved on INIT (doesn't touch the enable bit), > and this snippet from the SDM more or less says the APIC ID is preserved when it's > disabled in IA32_APIC_BASE. > > From the disabled state, the only valid x2APIC transition using IA32_APIC_BASE > is to the xAPIC mode (EN= 1, EXTD = 0). Thus the only means to transition from > x2APIC mode to xAPIC mode is a two-step process: > > - first transition from x2APIC mode to local APIC disabled mode (EN= 0, EXTD = 0), > - followed by another transition from disabled mode to xAPIC mode (EN= 1, EXTD= 0). > > Consequently, all the APIC register states in the x2APIC, except for the x2APIC ID > (32 bits), are not preserved across mode transitions. > > And for RESET vs. INIT > > A reset in this state places the x2APIC in xAPIC mode. All APIC registers > (including the local APIC ID register) are initialized as described in Section > 10.12.5.1. > > An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the > local APIC ID register is preserved (all 32 bits). However, all the other APIC > registers are initialized as a result of the INIT transition. > > Emanuele, what is the actual issue you are trying to fix? E.g. is APICv left > inihibited after an emulated RESET? Something else? I think the test in patch 2 I wrote gives a better idea on what I am trying to fix: if we are transitioning from x2APIC to xAPIC (RESET I would say, even though I am not sure if userspace really does it in the way I do it in the test, ie through KVM_SET_MSRS), the APIC_ID is not updated back in the right bits, and we can see that by querying the ID with KVM_GET_LAPIC after disabling x2APIC. Now, if the way I reproduce this issue is correct, it is indeed a bug and needs to be fixed with the fix in patch 1 or something similar. I think it won't really make any difference if instead following what the doc says (x2APIC -> disabled -> xAPIC) we directly do x2APIC -> xAPIC. The test in patch 2 started being developed to test ef40757743b47 ("KVM: x86: fix APICv/x2AVIC disabled when vm reboot by itself") even though I honestly didn't really understand how to replicate that bug (see cover letter) and instead I found this other possibility that still manages to screw APIC_ID. Hope this clarifies it a little, Emanuele Stuffing APIC state from > userspace should do the right thing after commit ef40757743b4 ("KVM: x86: fix > APICv/x2AVIC disabled when vm reboot by itself") and this patch: > > https://lore.kernel.org/all/20230106011306.85230-33-seanjc@google.com >
On 1/10/23 13:16, Emanuele Giuseppe Esposito wrote: > I think the test in patch 2 I wrote gives a better idea on what I am > trying to fix: if we are transitioning from x2APIC to xAPIC (RESET I > would say, even though I am not sure if userspace really does it in the > way I do it in the test, ie through KVM_SET_MSRS), the APIC_ID is not > updated back in the right bits, and we can see that by querying the ID > with KVM_GET_LAPIC after disabling x2APIC. > > Now, if the way I reproduce this issue is correct, it is indeed a bug > and needs to be fixed with the fix in patch 1 or something similar. > I think it won't really make any difference if instead following what > the doc says (x2APIC -> disabled -> xAPIC) we directly do x2APIC -> xAPIC. Yes, the default value at reset is xAPIC mode, so a reset will do a KVM_SET_MSRS that clears X2APIC_ENABLE but leaves MSR_IA32_APICBASE_ENABLE set. So, if I understand correctly... > The test in patch 2 started being developed to test ef40757743b47 ("KVM: > x86: fix APICv/x2AVIC disabled when vm reboot by itself") even though I > honestly didn't really understand how to replicate that bug (see cover > letter) and instead I found this other possibility that still manages to > screw APIC_ID. ... what you're saying is that there were two different bugs, but one fixing any one of them was enough to prevent the symptoms shown by commit ef40757743b47? That is: - the APICv inhibit was set by KVM_GET_LAPIC because it called kvm_lapic_xapic_id_updated(), and the call was unnecessary as fixed in commit ef40757743b47; - however, there is no reason for the vCPU ID to be mismatched. It happened because the code didn't handle the host-initiated x2APIC->xAPIC case and thus lacked a call to kvm_apic_set_xapic_id(). If so, I think the idea of the patch is fine. Just one thing: your patch also changes the APIC_ID on the x2APIC->disabled transition, not just the "forbidden" (i.e. host- initiated only) x2APIC->xAPIC transition. I think this is okay too: the manual says: 10.4.3 Enabling or Disabling the Local APIC When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may be lost and the APIC may return to the state described in Section 10.4.7.1, “Local APIC State After Power-Up or Reset.” 10.4.7.1 Local APIC State After Power-Up or Reset ... The local APIC ID register is set to a unique APIC ID. ... (which must be an xAPIC ID) and this is what your patch does. In fact perhaps you can change the code further to invoke kvm_lapic_reset() after static_branch_inc(&apic_hw_disabled.key)? It's just a bit messy that you have a call back to kvm_lapic_set_base() in there, so perhaps something like this can help: diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4efdb4a4d72c..24e5df23a4d9 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2433,9 +2436,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) { - struct kvm_lapic *apic = vcpu->arch.apic; u64 msr_val; - int i; if (!init_event) { msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; @@ -2444,8 +2445,14 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) kvm_lapic_set_base(vcpu, msr_val); } - if (!apic) - return; + if (vcpu->arch.apic) + __kvm_lapic_reset(vcpu, init_event); +} + +static void __kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) +{ + struct kvm_lapic *apic = vcpu->arch.apic; + int i; /* Stop the timer in case it's a reset to an active apic */ hrtimer_cancel(&apic->lapic_timer.timer); (just a sketch to show the idea, of course __kvm_lapic_reset would have to go first). Paolo
Am 10/01/2023 um 15:07 schrieb Paolo Bonzini: > On 1/10/23 13:16, Emanuele Giuseppe Esposito wrote: >> I think the test in patch 2 I wrote gives a better idea on what I am >> trying to fix: if we are transitioning from x2APIC to xAPIC (RESET I >> would say, even though I am not sure if userspace really does it in the >> way I do it in the test, ie through KVM_SET_MSRS), the APIC_ID is not >> updated back in the right bits, and we can see that by querying the ID >> with KVM_GET_LAPIC after disabling x2APIC. >> >> Now, if the way I reproduce this issue is correct, it is indeed a bug >> and needs to be fixed with the fix in patch 1 or something similar. >> I think it won't really make any difference if instead following what >> the doc says (x2APIC -> disabled -> xAPIC) we directly do x2APIC -> >> xAPIC. > > Yes, the default value at reset is xAPIC mode, so a reset will do a > KVM_SET_MSRS that clears X2APIC_ENABLE but leaves > MSR_IA32_APICBASE_ENABLE set. > > So, if I understand correctly... > >> The test in patch 2 started being developed to test ef40757743b47 ("KVM: >> x86: fix APICv/x2AVIC disabled when vm reboot by itself") even though I >> honestly didn't really understand how to replicate that bug (see cover >> letter) and instead I found this other possibility that still manages to >> screw APIC_ID. > > ... what you're saying is that there were two different bugs, but one > fixing any one of them was enough to prevent the symptoms shown by > commit ef40757743b47? That is: > > - the APICv inhibit was set by KVM_GET_LAPIC because it called > kvm_lapic_xapic_id_updated(), and the call was unnecessary as fixed in > commit ef40757743b47; > > - however, there is no reason for the vCPU ID to be mismatched. It > happened because the code didn't handle the host-initiated x2APIC->xAPIC > case and thus lacked a call to kvm_apic_set_xapic_id(). > > If so, I think the idea of the patch is fine. Yes :) > > Just one thing: your patch also changes the APIC_ID on the > x2APIC->disabled transition, not just the "forbidden" (i.e. host- > initiated only) x2APIC->xAPIC transition. I think this is okay too: the > manual says: > > 10.4.3 Enabling or Disabling the Local APIC > > When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC > may be lost and the APIC may return to the state described in Section > 10.4.7.1, “Local APIC State After Power-Up or Reset.” > > 10.4.7.1 Local APIC State After Power-Up or Reset > > ... The local APIC ID register is set to a unique APIC ID. ... > > (which must be an xAPIC ID) and this is what your patch does. > > In fact perhaps you can change the code further to invoke > kvm_lapic_reset() after static_branch_inc(&apic_hw_disabled.key)? Ok, it makes sense. In that case we are disabling lapic (X2APIC_ENABLE should be 0 too, otherwise it would be invalid. xAPIC global enable(IA32_APIC_BASE[11]) | x2APIC enable(IA32_APIC_BASE[10]) | Description 0 0 local APIC is disabled 0 1 Invalid 1 0 local APIC is enabled in xAPIC mode 1 1 local APIC is enabled in x2APIC mode Thank you, Emanuele It's > just a bit messy that you have a call back to kvm_lapic_set_base() in > there, so perhaps something like this can help: > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 4efdb4a4d72c..24e5df23a4d9 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2433,9 +2436,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) > > void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) > { > - struct kvm_lapic *apic = vcpu->arch.apic; > u64 msr_val; > - int i; > > if (!init_event) { > msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; > @@ -2444,8 +2445,14 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool > init_event) > kvm_lapic_set_base(vcpu, msr_val); > } > > - if (!apic) > - return; > + if (vcpu->arch.apic) > + __kvm_lapic_reset(vcpu, init_event); > +} > + > +static void __kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) > +{ > + struct kvm_lapic *apic = vcpu->arch.apic; > + int i; > > /* Stop the timer in case it's a reset to an active apic */ > hrtimer_cancel(&apic->lapic_timer.timer); > > > (just a sketch to show the idea, of course __kvm_lapic_reset would have to > go first). > > Paolo >
On Tue, Jan 10, 2023, Paolo Bonzini wrote: > On 1/10/23 13:16, Emanuele Giuseppe Esposito wrote: > > I think the test in patch 2 I wrote gives a better idea on what I am > > trying to fix: Tests and descriptions of expected s vs. actual behavior explain what _you_ think should happen, but don't help explain what higher level bug is being fixed. IIUC, QEMU emulates RESET and expects the xAPIC ID to be re-initialized. That's the info that should be provided in the changelog since it ties KVM behavior to a real world userspace emulating actual hardware behavior. > > if we are transitioning from x2APIC to xAPIC (RESET I > > would say, even though I am not sure if userspace really does it in the > > way I do it in the test, ie through KVM_SET_MSRS), the APIC_ID is not > > updated back in the right bits, and we can see that by querying the ID > > with KVM_GET_LAPIC after disabling x2APIC. > > > > Now, if the way I reproduce this issue is correct, it is indeed a bug > > and needs to be fixed with the fix in patch 1 or something similar. > > I think it won't really make any difference if instead following what > > the doc says (x2APIC -> disabled -> xAPIC) we directly do x2APIC -> xAPIC. > > Yes, the default value at reset is xAPIC mode, so a reset will do a > KVM_SET_MSRS that clears X2APIC_ENABLE but leaves > MSR_IA32_APICBASE_ENABLE set. > > So, if I understand correctly... > > > The test in patch 2 started being developed to test ef40757743b47 ("KVM: > > x86: fix APICv/x2AVIC disabled when vm reboot by itself") even though I > > honestly didn't really understand how to replicate that bug (see cover > > letter) and instead I found this other possibility that still manages to > > screw APIC_ID. > > ... what you're saying is that there were two different bugs, but one > fixing any one of them was enough to prevent the symptoms shown by > commit ef40757743b47? That is: > > - the APICv inhibit was set by KVM_GET_LAPIC because it called > kvm_lapic_xapic_id_updated(), and the call was unnecessary as fixed in > commit ef40757743b47; > > - however, there is no reason for the vCPU ID to be mismatched. It > happened because the code didn't handle the host-initiated x2APIC->xAPIC > case and thus lacked a call to kvm_apic_set_xapic_id(). > > If so, I think the idea of the patch is fine. > > Just one thing: your patch also changes the APIC_ID on the > x2APIC->disabled transition, not just the "forbidden" (i.e. host- > initiated only) x2APIC->xAPIC transition. I think this is okay too: the > manual says: > > 10.4.3 Enabling or Disabling the Local APIC > > When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC > may be lost and the APIC may return to the state described in Section > 10.4.7.1, “Local APIC State After Power-Up or Reset.” > > 10.4.7.1 Local APIC State After Power-Up or Reset > > ... The local APIC ID register is set to a unique APIC ID. ... > > (which must be an xAPIC ID) and this is what your patch does. Ugh, couldn't find that yesterday. It's actually irrelevant though, KVM already stuffs the APIC ID when the APIC goes from DISABLED to ENABLED (xAPIC) since commit: 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC") For giggles, and because I misread that like 5 times, I tested on hardware. Intel CPUs since at least Haswell make the APIC ID read-only, i.e. it's a moot point on Intel these days. But on AMD, the APIC ID is preserved across disabling => enabling xAPIC. > In fact perhaps you can change the code further to invoke > kvm_lapic_reset() after static_branch_inc(&apic_hw_disabled.key)? It's > just a bit messy that you have a call back to kvm_lapic_set_base() in > there, so perhaps something like this can help: I'd rather not touch kvm_lapic_reset(). KVM doesn't emulate RESET, and I don't want to make assumptions about why userspace is forcing x2APIC => xAPIC. If userspace wants to propery emulate RESET, it can use KVM_SET_LAPIC. My preference is to do a light tweak on the original patch, with a rewritten shortlog and changelog. And because I spent way, way too much time digging into this, I went a bit overboard... From: Sean Christopherson <seanjc@google.com> Date: Tue, 10 Jan 2023 10:40:33 -0800 Subject: [PATCH] KVM: x86: Reinitialize xAPIC ID when userspace forces x2APIC => xAPIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reinitialize the xAPIC ID to the vCPU ID when userspace forces the APIC to transition directly from x2APIC to xAPIC mode, e.g. to emulate RESET. KVM already stuffs the xAPIC ID when the APIC is transitioned from DISABLED to xAPIC (commit 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC")), i.e. userspace is conditioned to expect KVM to update the xAPIC ID, but KVM doesn't handle the architecturally-impossible case where userspace forces x2APIC=>xAPIC via KVM_SET_MSRS. On its own, the "bug" is benign, as userspace emulation of RESET will also stuff APIC registers via KVM_SET_LAPIC, i.e. will manually set the xAPIC ID. However, commit 3743c2f02517 ("KVM: x86: inhibit APICv/AVIC on changes to APIC ID or APIC base") introduced a bug, fixed by commit commit ef40757743b4 ("KVM: x86: fix APICv/x2AVIC disabled when vm reboot by itself"), that caused KVM to fail to properly update the xAPIC ID when handling KVM_SET_LAPIC. Refresh the xAPIC ID even though it's not strictly necessary so that KVM provides consistent behavior. Note, KVM follows Intel architecture with regard to handling the xAPIC ID and x2APIC IDs across mode transitions. For the APIC DISABLED case (commit 49bd29ba1dbd), Intel's SDM says the xAPIC ID _may_ be reinitialized 10.4.3 Enabling or Disabling the Local APIC When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may be lost and the APIC may return to the state described in Section 10.4.7.1, “Local APIC State After Power-Up or Reset.” 10.4.7.1 Local APIC State After Power-Up or Reset ... The local APIC ID register is set to a unique APIC ID. ... i.e. KVM's behavior is legal as per Intel's architecture. In practice, Intel's behavior is N/A as modern Intel CPUs (since at least Haswell) make the xAPIC ID fully read-only. And for xAPIC => x2APIC transitions (commit 257b9a5faab5 ("KVM: x86: use correct APIC ID on x2APIC transition")), Intel's SDM says: Any APIC ID value written to the memory-mapped local APIC ID register is not preserved. AMD's APM says nothing (that I could find) about the xAPIC ID when the APIC is DISABLED, but testing on bare metal (Rome) shows that the xAPIC ID is preserved when the APIC is DISABLED and re-enabled in xAPIC mode. AMD also preserves the xAPIC ID when the APIC is transitioned from xAPIC to x2APIC, i.e. allows a backdoor write of the x2APIC ID, which is again not emulated by KVM. Reported-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Sean Christopherson <seanjc@google.com> --- arch/x86/kvm/lapic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 80f92cbc4029..79141d76ad49 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2485,8 +2485,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) } } - if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) - kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); + if ((old_value ^ value) & X2APIC_ENABLE) { + if (value & X2APIC_ENABLE) + kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); + else if (value & MSR_IA32_APICBASE_ENABLE) + kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); + } if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); base-commit: 91dc252b0dbb6879e4067f614df1e397fec532a1 --
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4efdb4a4d72c..df0a50099aa2 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2394,8 +2394,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) } } - if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) - kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); + if ((old_value ^ value) & X2APIC_ENABLE) { + if (value & X2APIC_ENABLE) + kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); + else + kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); + } if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { kvm_vcpu_update_apicv(vcpu);
If KVM_SET_MSR firstly enables and then disables x2APIC, make sure APIC_ID is actually updated correctly, since bits and offset differ from xAPIC and x2APIC. Currently this is not handled correctly, as kvm_set_apic_base() will have msr_info->host_initiated, so switching from x2APIC to xAPIC won't fail, but kvm_lapic_set_base() does not handle the case. Fixes: 8d860bbeedef ("kvm: vmx: Basic APIC virtualization controls have three settings") Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> --- arch/x86/kvm/lapic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)