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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 5/6] Documentation: amd-pstate: introduce AMD Pstate Preferred Core Date: Tue, 8 Aug 2023 16:10:00 +0800 Message-ID: <20230808081001.2215240-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|DS0PR12MB7850:EE_ X-MS-Office365-Filtering-Correlation-Id: e5a7daef-589a-476c-cb13-08db97e7169d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IWb6XxjF625mNZLRF3t+HUs8Isfb387RRx8nm8QYO1UxjzusdxVMrp4AfLpKy9EPOIPsf8oVQvO3ZRV8ZXsenLY+DkW3BtLigx4H3Bz4/5a2npCeIJJDFgmIRxwfcdCHlo4e1xRkniclgmiUZvF72sR1HTzOfPC7rMGKSiJgjuvLWI8H+hWMc9AXUbpD9gqqbfmEMqCKIHWEQgqL1JgAQWH7CGtaLi/a5LAFhtc6qXmSNv64dxcn0+z3LuT5YlZuQKnvDyae3u0It8GLpD/x2RDphz8XTR4Ogol9/UG5UV0MMAJLLEnv0umbOpoUVm4Tjag1iv4iUjKOP0F8/t7TJ/nn2JqfWnN5Ak6xyskUuusuPnC2NnK/xSRZG/HuLO2ALagJgOH5uAs1QvU9pHIir/MsztwIZctuzniNqBDYYgTzTGe1Nfg1tB67GuWetrtG4X25aCSc+V3qJqumPNTQQ/gjTjyrtdG3tx8/pa3n8CVBzPGZ99ZU62T9do8bwMeDELisHRPAVR0DfbA1dziCQwPGiG8stx8wcFjwYAYajzAV3LGdmjM+PZfQAhrZnk8WVaBtOxa+OdQyfaRzS6p4FHyP9QrhJmICpmaSwEsM56mc7xs3SqaAa/8ozB2t3E5M260MBTM92JuJvssEbK1LaHzi7TBR525Ovg4vGUpvY+NcbujCADq/x3XZGqSRnrg/Ey9M8NvmINe9OOZSAcxdb1mSPQjDSpvEBbLfJncErzw2DHrOejXv3g2S3bJiVw/oPTm+9GRywka9TM1X9XtnTVLwVUoN3ZQoADlaeg1r9u0nWHXzaaVTUzR5t82cSA6OQ9rYUnixnkiMaJZSVMi5lA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(39860400002)(396003)(136003)(90021799007)(82310400008)(1800799003)(186006)(451199021)(90011799007)(46966006)(36840700001)(40470700004)(426003)(1076003)(41300700001)(26005)(2906002)(5660300002)(83380400001)(8676002)(36860700001)(47076005)(8936002)(16526019)(40460700003)(2616005)(40480700001)(336012)(81166007)(478600001)(316002)(7696005)(356005)(54906003)(70206006)(110136005)(70586007)(82740400003)(6666004)(6636002)(86362001)(4326008)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:11:37.4174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5a7daef-589a-476c-cb13-08db97e7169d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7850 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Introduce AMD Pstate Preferred Core. check preferred core state: $ cat /sys/devices/system/cpu/amd-pstate/prefcore_state Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 55 +++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..4a30cf235425 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -353,6 +353,49 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +AMD Pstate Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``AMD Pstate Preferred Core`` use ITMT arch provides functions and data structures +for enabling the scheduler to favor scheduling on cores can be get a higher frequency +with lower voltage under preferred core. And it has the ability to dynamically +change the preferred core based on the workload and platform conditions and +accounting for thermals and aging. + +The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate +driver will also determine whether or not ``AMD Pstate Preferred Core`` is +supported by the platform. + +AMD Pstate driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When AMD Pstate +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +AMD Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``AMD Pstate Preferred Core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default disable ``AMD Pstate Preferred Core``. + +``amd_prefcore=enable`` + +If ``amd_prefcore=enable`` is passed to kernel command line option +then enable ``AMD Pstate Preferred Core`` if the processor and power +firmware can support preferred core feature. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +428,18 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore_state`` + Preferred Core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the AMD Preferred Core. + + "disabled" + Disable the AMD Preferred Core + + + This attribute is read-only to check the state of Preferred Core. + ``cpupower`` tool support for ``amd-pstate`` ===============================================