diff mbox series

[v8,09/10] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation

Message ID 20231227161354.67701-10-yi.l.liu@intel.com (mailing list archive)
State New
Headers show
Series Add iommufd nesting (part 2/2) | expand

Commit Message

Yi Liu Dec. 27, 2023, 4:13 p.m. UTC 
This adds the data structure invalidating caches for the nested domain
allocated with IOMMU_HWPT_DATA_VTD_S1 type.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
---
 include/uapi/linux/iommufd.h | 55 ++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

Comments

Tian, Kevin Dec. 28, 2023, 6:37 a.m. UTC | #1 
> From: Liu, Yi L <yi.l.liu@intel.com>
> Sent: Thursday, December 28, 2023 12:14 AM
> +/**
> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
> + *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
> + * @addr: The start address of the range to be invalidated. It needs to
> + *        be 4KB aligned.
> + * @npages: Number of contiguous 4K pages to be invalidated.
> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
> + * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error
> + *
> + * The Intel VT-d specific invalidation data for user-managed stage-1 cache
> + * invalidation in nested translation. Userspace uses this structure to
> + * tell the impacted cache scope after modifying the stage-1 page table.
> + *
> + * Invalidating all the caches related to the page table by setting @addr
> + * to be 0 and @npages to be U64_MAX.
> + *
> + * The device TLB will be invalidated automatically if ATS is enabled.
> + *
> + * The @hw_error is meaningful when the entry is handled by the kernel.
> + * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to
> know the
> + * handled entries. @hw_error only covers the errors detected by hardware.
> + * The software detected errors would go through the normal ioctl errno.
> + */

* An entry is considered 'handled' after it passes the audit and submitted
* to the IOMMU by the underlying driver. Check the @entry_num output of
* struct iommu_hwpt_invalidate for the number of handled entries. A 'handled'
* request may still fail in hardware for various reasons, e.g. due to timeout
* on waiting for device response upon a device TLB invalidation request. In
* such case the hardware error info is reported in the @hw_error field of the
* handled entry.
Tian, Kevin Dec. 28, 2023, 6:38 a.m. UTC | #2 
> From: Tian, Kevin
> Sent: Thursday, December 28, 2023 2:38 PM
> 
> > From: Liu, Yi L <yi.l.liu@intel.com>
> > Sent: Thursday, December 28, 2023 12:14 AM
> > +/**
> > + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
> > + *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
> > + * @addr: The start address of the range to be invalidated. It needs to
> > + *        be 4KB aligned.
> > + * @npages: Number of contiguous 4K pages to be invalidated.
> > + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
> > + * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error
> > + *
> > + * The Intel VT-d specific invalidation data for user-managed stage-1 cache
> > + * invalidation in nested translation. Userspace uses this structure to
> > + * tell the impacted cache scope after modifying the stage-1 page table.
> > + *
> > + * Invalidating all the caches related to the page table by setting @addr
> > + * to be 0 and @npages to be U64_MAX.
> > + *
> > + * The device TLB will be invalidated automatically if ATS is enabled.
> > + *
> > + * The @hw_error is meaningful when the entry is handled by the kernel.
> > + * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to
> > know the
> > + * handled entries. @hw_error only covers the errors detected by
> hardware.
> > + * The software detected errors would go through the normal ioctl errno.
> > + */
> 
> * An entry is considered 'handled' after it passes the audit and submitted
> * to the IOMMU by the underlying driver. Check the @entry_num output of
> * struct iommu_hwpt_invalidate for the number of handled entries. A
> 'handled'
> * request may still fail in hardware for various reasons, e.g. due to timeout
> * on waiting for device response upon a device TLB invalidation request. In
> * such case the hardware error info is reported in the @hw_error field of the
> * handled entry.

with that:

Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Yi Liu Dec. 28, 2023, 8:35 a.m. UTC | #3 
On 2023/12/28 14:38, Tian, Kevin wrote:
>> From: Tian, Kevin
>> Sent: Thursday, December 28, 2023 2:38 PM
>>
>>> From: Liu, Yi L <yi.l.liu@intel.com>
>>> Sent: Thursday, December 28, 2023 12:14 AM
>>> +/**
>>> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
>>> + *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
>>> + * @addr: The start address of the range to be invalidated. It needs to
>>> + *        be 4KB aligned.
>>> + * @npages: Number of contiguous 4K pages to be invalidated.
>>> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
>>> + * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error
>>> + *
>>> + * The Intel VT-d specific invalidation data for user-managed stage-1 cache
>>> + * invalidation in nested translation. Userspace uses this structure to
>>> + * tell the impacted cache scope after modifying the stage-1 page table.
>>> + *
>>> + * Invalidating all the caches related to the page table by setting @addr
>>> + * to be 0 and @npages to be U64_MAX.
>>> + *
>>> + * The device TLB will be invalidated automatically if ATS is enabled.
>>> + *
>>> + * The @hw_error is meaningful when the entry is handled by the kernel.
>>> + * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to
>>> know the
>>> + * handled entries. @hw_error only covers the errors detected by
>> hardware.
>>> + * The software detected errors would go through the normal ioctl errno.
>>> + */
>>
>> * An entry is considered 'handled' after it passes the audit and submitted
>> * to the IOMMU by the underlying driver. Check the @entry_num output of
>> * struct iommu_hwpt_invalidate for the number of handled entries. A
>> 'handled'
>> * request may still fail in hardware for various reasons, e.g. due to timeout
>> * on waiting for device response upon a device TLB invalidation request. In
>> * such case the hardware error info is reported in the @hw_error field of the
>> * handled entry.
> 
> with that:
> 
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>

yep.
diff mbox series

Patch

diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
index 824560c50ec6..2067aa00d2a3 100644
--- a/include/uapi/linux/iommufd.h
+++ b/include/uapi/linux/iommufd.h
@@ -623,6 +623,61 @@  enum iommu_hwpt_invalidate_data_type {
 	IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
 };
 
+/**
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
+ *                                           stage-1 cache invalidation
+ * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
+ *                            to all-levels page structure cache or just
+ *                            the leaf PTE cache.
+ */
+enum iommu_hwpt_vtd_s1_invalidate_flags {
+	IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
+};
+
+/**
+ * enum iommu_hwpt_vtd_s1_invalidate_error - Hardware error of invalidation
+ * @IOMMU_HWPT_INVALIDATE_VTD_S1_ICE: Invalidation Completion Error, details
+ *                                    refer to 11.4.7.1 Fault Status Register
+ *                                    of VT-d specification.
+ * @IOMMU_HWPT_INVALIDATE_VTD_S1_ITE: Invalidation Time-out Error, details
+ *                                    refer to 11.4.7.1 Fault Status Register
+ *                                    of VT-d specification.
+ */
+enum iommu_hwpt_vtd_s1_invalidate_error {
+	IOMMU_HWPT_INVALIDATE_VTD_S1_ICE = 1 << 0,
+	IOMMU_HWPT_INVALIDATE_VTD_S1_ITE = 1 << 1,
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
+ *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
+ * @addr: The start address of the range to be invalidated. It needs to
+ *        be 4KB aligned.
+ * @npages: Number of contiguous 4K pages to be invalidated.
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
+ * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error
+ *
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
+ * invalidation in nested translation. Userspace uses this structure to
+ * tell the impacted cache scope after modifying the stage-1 page table.
+ *
+ * Invalidating all the caches related to the page table by setting @addr
+ * to be 0 and @npages to be U64_MAX.
+ *
+ * The device TLB will be invalidated automatically if ATS is enabled.
+ *
+ * The @hw_error is meaningful when the entry is handled by the kernel.
+ * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to know the
+ * handled entries. @hw_error only covers the errors detected by hardware.
+ * The software detected errors would go through the normal ioctl errno.
+ */
+struct iommu_hwpt_vtd_s1_invalidate {
+	__aligned_u64 addr;
+	__aligned_u64 npages;
+	__u32 flags;
+	__u32 hw_error;
+};
+
 /**
  * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
  * @size: sizeof(struct iommu_hwpt_invalidate)