From patchwork Tue Jan 16 06:01:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaoqin Huang X-Patchwork-Id: 13520456 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A6411712 for ; Tue, 16 Jan 2024 06:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="hJcSKHPd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1705384901; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U9F5YnPtqeaOtnF1jbWP/C35kmOg9rX0z8z8z6VZYAU=; b=hJcSKHPdW4XrR9Gje6q5+FIAIWQM3CPzbzWzEpQ65C7MBTmId2UgfWXVywgr//NFtGcHYZ Ef92X8t1X+xTFgBq9znphMdsl+gO3GaKPR2KZ4xdCIsG0MicBXMFfh7IgsZUKYcXyoFAZw 7tVZyzZvkwCXTBDdWcRptR79bMdqWkE= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-341-Myyr4p0TPemJrsDxd090_Q-1; Tue, 16 Jan 2024 01:01:35 -0500 X-MC-Unique: Myyr4p0TPemJrsDxd090_Q-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B8CE01C05ABF; Tue, 16 Jan 2024 06:01:34 +0000 (UTC) Received: from virt-mtcollins-01.lab.eng.rdu2.redhat.com (virt-mtcollins-01.lab.eng.rdu2.redhat.com [10.8.1.196]) by smtp.corp.redhat.com (Postfix) with ESMTP id A5B1B2026D6F; Tue, 16 Jan 2024 06:01:34 +0000 (UTC) From: Shaoqin Huang To: Oliver Upton , Marc Zyngier , kvmarm@lists.linux.dev Cc: Eric Auger , Shaoqin Huang , Eric Auger , James Morse , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] KVM: selftests: aarch64: Fix the buggy [enable|disable]_counter Date: Tue, 16 Jan 2024 01:01:21 -0500 Message-Id: <20240116060129.55473-4-shahuang@redhat.com> In-Reply-To: <20240116060129.55473-1-shahuang@redhat.com> References: <20240116060129.55473-1-shahuang@redhat.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.4 In general, the set/clr registers should always be used in their write form, never in a RMW form (imagine an interrupt disabling a counter between the read and the write...). The current implementation of [enable|disable]_counter both use the RMW form, fix them by directly write to the set/clr registers. At the same time, it also fix the buggy disable_counter() which would end up disabling all the counters. Reviewed-by: Eric Auger Signed-off-by: Shaoqin Huang --- tools/testing/selftests/kvm/include/aarch64/vpmu.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/include/aarch64/vpmu.h b/tools/testing/selftests/kvm/include/aarch64/vpmu.h index e0cc1ca1c4b7..644dae3814b5 100644 --- a/tools/testing/selftests/kvm/include/aarch64/vpmu.h +++ b/tools/testing/selftests/kvm/include/aarch64/vpmu.h @@ -78,17 +78,13 @@ static inline void write_sel_evtyper(int sel, unsigned long val) static inline void enable_counter(int idx) { - uint64_t v = read_sysreg(pmcntenset_el0); - - write_sysreg(BIT(idx) | v, pmcntenset_el0); + write_sysreg(BIT(idx), pmcntenset_el0); isb(); } static inline void disable_counter(int idx) { - uint64_t v = read_sysreg(pmcntenset_el0); - - write_sysreg(BIT(idx) | v, pmcntenclr_el0); + write_sysreg(BIT(idx), pmcntenclr_el0); isb(); }