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riscv: Support vendor extensions and xtheadvector
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expand
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diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 13bc99c995d1..e5a35efd56e0 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -219,6 +219,8 @@ #define VCSR_VXRM_MASK 3 #define VCSR_VXRM_SHIFT 1 #define VCSR_VXSAT_MASK 1 +#define VCSR_VXSAT 0x9 +#define VCSR_VXRM 0xa /* symbolic CSR names: */ #define CSR_CYCLE 0xc00
The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 ++ 1 file changed, 2 insertions(+)