| Message ID | 20240426-dev-charlie-support_thead_vector_6_9-v4-6-b692f3c516ec@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Support vendor extensions and xtheadvector | expand |
On Fri, Apr 26, 2024 at 02:29:20PM -0700, Charlie Jenkins wrote: > index c073494519eb..dd7e8e0c0af1 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -844,25 +844,41 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, > { > struct alt_entry *alt; > void *oldptr, *altptr; > - u16 id, value; > + u16 id, value, vendor; > > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) > return; > > for (alt = begin; alt < end; alt++) { > - if (alt->vendor_id != 0) > - continue; > - > id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); > + vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); > > - if (id >= RISCV_ISA_EXT_MAX) { > + /* > + * Any alternative with a patch_id that is less than > + * RISCV_ISA_EXT_MAX is interpreted as a standard extension. > + * > + * Any alternative with patch_id that is greater than or equal > + * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a > + * vendor extension. I think this stuff is all fine, since we can always re-jig things in the future if needs be. > + */ > + if (id < RISCV_ISA_EXT_MAX) { > + /* > + * This patch should be treated as errata so skip > + * processing here. > + */ > + if (alt->vendor_id != 0) > + continue; > + > + if (!__riscv_isa_extension_available(NULL, id)) > + continue; > + } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { > + if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, id)) > + continue; > + } else { > WARN(1, "This extension id:%d is not in ISA extension list", id); > continue; > } > > - if (!__riscv_isa_extension_available(NULL, id)) > - continue; > - > value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); > if (!riscv_cpufeature_patch_check(id, value)) > continue; > diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c > index f76cb3013c2d..eced93eec5a6 100644 > --- a/arch/riscv/kernel/vendor_extensions.c > +++ b/arch/riscv/kernel/vendor_extensions.c > @@ -3,6 +3,7 @@ > * Copyright 2024 Rivos, Inc > */ > > +#include <asm/vendorid_list.h> > #include <asm/vendor_extensions.h> > #include <asm/vendor_extensions/thead.h> > > @@ -16,3 +17,42 @@ const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { > }; > > const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list); > + > +/** > + * __riscv_isa_vendor_extension_available() - Check whether given vendor > + * extension is available or not. > + * > + * @cpu: check if extension is available on this cpu > + * @vendor: vendor that the extension is a member of > + * @bit: bit position of the desired extension > + * Return: true or false > + * > + * NOTE: When cpu is -1, will check if extension is available on all cpus > + */ > +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit) > +{ > + unsigned long *bmap; > + struct riscv_isainfo *cpu_bmap; > + size_t bmap_size; > + > + switch (vendor) { > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > + case THEAD_VENDOR_ID: > + bmap = riscv_isa_vendor_ext_list_thead.vendor_bitmap; > + cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; > + bmap_size = riscv_isa_vendor_ext_list_thead.bitmap_size; > + break; > +#endif > + default: > + return false; > + } > + > + if (cpu != -1) > + bmap = cpu_bmap[cpu].isa; > + > + if (bit >= bmap_size) > + return false; > + > + return test_bit(bit, bmap) ? true : false; > +} > +EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available); I wonder if we care to implement a non __ prefixed version of this, like the standard stuff? The only __ version users of the standard one are in kvm and core arch code, the "external" users all use the non-prefixed version. In any case, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Wed, May 01, 2024 at 12:29:56PM +0100, Conor Dooley wrote: > On Fri, Apr 26, 2024 at 02:29:20PM -0700, Charlie Jenkins wrote: > > > index c073494519eb..dd7e8e0c0af1 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -844,25 +844,41 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, > > { > > struct alt_entry *alt; > > void *oldptr, *altptr; > > - u16 id, value; > > + u16 id, value, vendor; > > > > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) > > return; > > > > for (alt = begin; alt < end; alt++) { > > - if (alt->vendor_id != 0) > > - continue; > > - > > id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); > > + vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); > > > > - if (id >= RISCV_ISA_EXT_MAX) { > > + /* > > + * Any alternative with a patch_id that is less than > > + * RISCV_ISA_EXT_MAX is interpreted as a standard extension. > > + * > > + * Any alternative with patch_id that is greater than or equal > > + * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a > > + * vendor extension. > > I think this stuff is all fine, since we can always re-jig things in the > future if needs be. > > > + */ > > + if (id < RISCV_ISA_EXT_MAX) { > > + /* > > + * This patch should be treated as errata so skip > > + * processing here. > > + */ > > + if (alt->vendor_id != 0) > > + continue; > > + > > + if (!__riscv_isa_extension_available(NULL, id)) > > + continue; > > + } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { > > + if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, id)) > > + continue; > > + } else { > > WARN(1, "This extension id:%d is not in ISA extension list", id); > > continue; > > } > > > > - if (!__riscv_isa_extension_available(NULL, id)) > > - continue; > > - > > value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); > > if (!riscv_cpufeature_patch_check(id, value)) > > continue; > > diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c > > index f76cb3013c2d..eced93eec5a6 100644 > > --- a/arch/riscv/kernel/vendor_extensions.c > > +++ b/arch/riscv/kernel/vendor_extensions.c > > @@ -3,6 +3,7 @@ > > * Copyright 2024 Rivos, Inc > > */ > > > > +#include <asm/vendorid_list.h> > > #include <asm/vendor_extensions.h> > > #include <asm/vendor_extensions/thead.h> > > > > @@ -16,3 +17,42 @@ const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { > > }; > > > > const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list); > > + > > +/** > > + * __riscv_isa_vendor_extension_available() - Check whether given vendor > > + * extension is available or not. > > + * > > + * @cpu: check if extension is available on this cpu > > + * @vendor: vendor that the extension is a member of > > + * @bit: bit position of the desired extension > > + * Return: true or false > > + * > > + * NOTE: When cpu is -1, will check if extension is available on all cpus > > + */ > > +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit) > > +{ > > + unsigned long *bmap; > > + struct riscv_isainfo *cpu_bmap; > > + size_t bmap_size; > > + > > + switch (vendor) { > > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > > + case THEAD_VENDOR_ID: > > + bmap = riscv_isa_vendor_ext_list_thead.vendor_bitmap; > > + cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; > > + bmap_size = riscv_isa_vendor_ext_list_thead.bitmap_size; > > + break; > > +#endif > > + default: > > + return false; > > + } > > + > > + if (cpu != -1) > > + bmap = cpu_bmap[cpu].isa; > > + > > + if (bit >= bmap_size) > > + return false; > > + > > + return test_bit(bit, bmap) ? true : false; > > +} > > +EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available); > > I wonder if we care to implement a non __ prefixed version of this, like > the standard stuff? The only __ version users of the standard one are in > kvm and core arch code, the "external" users all use the non-prefixed > version. In vendor_extensions.h there is: #define riscv_isa_vendor_extension_available(vendor, ext) \ __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ RISCV_ISA_VENDOR_EXT_##ext) > > In any case, > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks! - Charlie > > Cheers, > Conor.
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 3d9a32d791f7..b68b023115c2 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -12,6 +12,7 @@ #include <asm/alternative.h> #include <asm/vendorid_list.h> #include <asm/errata_list.h> +#include <asm/vendor_extensions.h> struct errata_info_t { char name[32]; @@ -91,6 +92,8 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, u32 cpu_apply_errata = 0; u32 tmp; + BUILD_BUG_ON(ERRATA_SIFIVE_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index b1c410bbc1ae..6d5d7f8eebbc 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <asm/patch.h> #include <asm/vendorid_list.h> +#include <asm/vendor_extensions.h> static bool errata_probe_pbmt(unsigned int stage, unsigned long arch_id, unsigned long impid) @@ -160,6 +161,8 @@ void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, u32 tmp; void *oldptr, *altptr; + BUILD_BUG_ON(ERRATA_THEAD_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + for (alt = begin; alt < end; alt++) { if (alt->vendor_id != THEAD_VENDOR_ID) continue; diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/include/asm/vendor_extensions.h index 0af1ddd0af70..74b82433e0a2 100644 --- a/arch/riscv/include/asm/vendor_extensions.h +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -23,4 +23,101 @@ extern const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[]; extern const size_t riscv_isa_vendor_ext_list_size; +/* + * The alternatives need some way of distinguishing between vendor extensions + * and errata. Incrementing all of the vendor extension keys so they are at + * least 0x8000 accomplishes that. + */ +#define RISCV_VENDOR_EXT_ALTERNATIVES_BASE 0x8000 + +#define VENDOR_EXT_ALL_CPUS -1 + +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit); +#define riscv_cpu_isa_vendor_extension_available(cpu, vendor, ext) \ + __riscv_isa_vendor_extension_available(cpu, vendor, RISCV_ISA_VENDOR_EXT_##ext) +#define riscv_isa_vendor_extension_available(vendor, ext) \ + __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ + RISCV_ISA_VENDOR_EXT_##ext) + +static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("j %l[l_no]", "nop", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("nop", "j %l[l_yes]", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + +static __always_inline bool riscv_has_vendor_extension_likely(const unsigned long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_likely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); +} + +static __always_inline bool riscv_has_vendor_extension_unlikely(const unsigned long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_unlikely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_likely(const unsigned long vendor, + int cpu, const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_likely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_unlikely(const unsigned long vendor, + int cpu, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_unlikely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + #endif /* _ASM_VENDOR_EXTENSIONS_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c073494519eb..dd7e8e0c0af1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -844,25 +844,41 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, { struct alt_entry *alt; void *oldptr, *altptr; - u16 id, value; + u16 id, value, vendor; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; for (alt = begin; alt < end; alt++) { - if (alt->vendor_id != 0) - continue; - id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); + vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); - if (id >= RISCV_ISA_EXT_MAX) { + /* + * Any alternative with a patch_id that is less than + * RISCV_ISA_EXT_MAX is interpreted as a standard extension. + * + * Any alternative with patch_id that is greater than or equal + * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a + * vendor extension. + */ + if (id < RISCV_ISA_EXT_MAX) { + /* + * This patch should be treated as errata so skip + * processing here. + */ + if (alt->vendor_id != 0) + continue; + + if (!__riscv_isa_extension_available(NULL, id)) + continue; + } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { + if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, id)) + continue; + } else { WARN(1, "This extension id:%d is not in ISA extension list", id); continue; } - if (!__riscv_isa_extension_available(NULL, id)) - continue; - value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); if (!riscv_cpufeature_patch_check(id, value)) continue; diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c index f76cb3013c2d..eced93eec5a6 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -3,6 +3,7 @@ * Copyright 2024 Rivos, Inc */ +#include <asm/vendorid_list.h> #include <asm/vendor_extensions.h> #include <asm/vendor_extensions/thead.h> @@ -16,3 +17,42 @@ const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { }; const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list); + +/** + * __riscv_isa_vendor_extension_available() - Check whether given vendor + * extension is available or not. + * + * @cpu: check if extension is available on this cpu + * @vendor: vendor that the extension is a member of + * @bit: bit position of the desired extension + * Return: true or false + * + * NOTE: When cpu is -1, will check if extension is available on all cpus + */ +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit) +{ + unsigned long *bmap; + struct riscv_isainfo *cpu_bmap; + size_t bmap_size; + + switch (vendor) { +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + case THEAD_VENDOR_ID: + bmap = riscv_isa_vendor_ext_list_thead.vendor_bitmap; + cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; + bmap_size = riscv_isa_vendor_ext_list_thead.bitmap_size; + break; +#endif + default: + return false; + } + + if (cpu != -1) + bmap = cpu_bmap[cpu].isa; + + if (bit >= bmap_size) + return false; + + return test_bit(bit, bmap) ? true : false; +} +EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available);
Vendor extensions are maintained in per-vendor structs (separate from standard extensions which live in riscv_isa). Create vendor variants for the existing extension helpers to interface with the riscv_isa_vendor bitmaps. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/errata/sifive/errata.c | 3 + arch/riscv/errata/thead/errata.c | 3 + arch/riscv/include/asm/vendor_extensions.h | 97 ++++++++++++++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 32 +++++++--- arch/riscv/kernel/vendor_extensions.c | 40 ++++++++++++ 5 files changed, 167 insertions(+), 8 deletions(-)