Message ID | 20240702-xtheadvector-v4-6-2bad6820db11@rivosinc.com (mailing list archive) |
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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240702-xtheadvector-v4-6-2bad6820db11@rivosinc.com> References: <20240702-xtheadvector-v4-0-2bad6820db11@rivosinc.com> In-Reply-To: <20240702-xtheadvector-v4-0-2bad6820db11@rivosinc.com> To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Samuel Holland <samuel.holland@sifive.com>, Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>, Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>, Andy Chiu <andy.chiu@sifive.com>, Jessica Clarke <jrtc27@jrtc27.com> Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins <charlie@rivosinc.com>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Heiko Stuebner <heiko@sntech.de> X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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riscv: Add support for xtheadvector
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diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..3eeb07d73065 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,6 +300,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151