Message ID | 20240722-xtheadvector-v6-7-c9af0130fa00@rivosinc.com (mailing list archive) |
---|---|
State | Accepted |
Commit | b9a9314424512e536db5e54ff554c2f10759c657 |
Headers | show
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riscv: Add support for xtheadvector
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diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 3eeb07d73065..c0a60c4ed911 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,9 +300,14 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D -#define VCSR_VXRM_MASK 3 -#define VCSR_VXRM_SHIFT 1 -#define VCSR_VXSAT_MASK 1 +/* xtheadvector symbolic CSR names */ +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa + +/* xtheadvector CSR masks */ +#define CSR_VXRM_MASK 3 +#define CSR_VXRM_SHIFT 1 +#define CSR_VXSAT_MASK 1 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150