| Message ID | 20250204-v5_user_cfi_series-v9-14-b37a49c5205c@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv control-flow integrity for usermode | expand |
On 05/02/2025 02:22, Deepak Gupta wrote: > zicfiss / zicfilp introduces a new exception to priv isa `software check > exception` with cause code = 18. This patch implements software check > exception. Hey Deepak, While not directly related to this patch, is the exception 18 delegation documented in the SBI doc ? I mean, should we specify that it is always delegated when implementing FWFT LANDING_PAD/SHADOW_STACK ? Thanks, Clément > > Additionally it implements a cfi violation handler which checks for code > in xtval. If xtval=2, it means that sw check exception happened because of > an indirect branch not landing on 4 byte aligned PC or not landing on > `lpad` instruction or label value embedded in `lpad` not matching label > value setup in `x7`. If xtval=3, it means that sw check exception happened > because of mismatch between link register (x1 or x5) and top of shadow > stack (on execution of `sspopchk`). > > In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR. > SEGV_CPERR was introduced by x86 shadow stack patches. > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > --- > arch/riscv/include/asm/asm-prototypes.h | 1 + > arch/riscv/include/asm/entry-common.h | 2 ++ > arch/riscv/kernel/entry.S | 3 +++ > arch/riscv/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++ > 4 files changed, 49 insertions(+) > > diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h > index cd627ec289f1..5a27cefd7805 100644 > --- a/arch/riscv/include/asm/asm-prototypes.h > +++ b/arch/riscv/include/asm/asm-prototypes.h > @@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u); > DECLARE_DO_ERROR_INFO(do_trap_ecall_s); > DECLARE_DO_ERROR_INFO(do_trap_ecall_m); > DECLARE_DO_ERROR_INFO(do_trap_break); > +DECLARE_DO_ERROR_INFO(do_trap_software_check); > > asmlinkage void handle_bad_stack(struct pt_regs *regs); > asmlinkage void do_page_fault(struct pt_regs *regs); > diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h > index b28ccc6cdeea..34ed149af5d1 100644 > --- a/arch/riscv/include/asm/entry-common.h > +++ b/arch/riscv/include/asm/entry-common.h > @@ -40,4 +40,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs) > } > #endif > > +bool handle_user_cfi_violation(struct pt_regs *regs); > + > #endif /* _ASM_RISCV_ENTRY_COMMON_H */ > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 00494b54ff4a..9c00cac3f6f2 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -472,6 +472,9 @@ SYM_DATA_START_LOCAL(excp_vect_table) > RISCV_PTR do_page_fault /* load page fault */ > RISCV_PTR do_trap_unknown > RISCV_PTR do_page_fault /* store page fault */ > + RISCV_PTR do_trap_unknown /* cause=16 */ > + RISCV_PTR do_trap_unknown /* cause=17 */ > + RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */ > SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) > > #ifndef CONFIG_MMU > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c > index 8ff8e8b36524..3f7709f4595a 100644 > --- a/arch/riscv/kernel/traps.c > +++ b/arch/riscv/kernel/traps.c > @@ -354,6 +354,49 @@ void do_trap_ecall_u(struct pt_regs *regs) > > } > > +#define CFI_TVAL_FCFI_CODE 2 > +#define CFI_TVAL_BCFI_CODE 3 > +/* handle cfi violations */ > +bool handle_user_cfi_violation(struct pt_regs *regs) > +{ > + bool ret = false; > + unsigned long tval = csr_read(CSR_TVAL); > + > + if ((tval == CFI_TVAL_FCFI_CODE && cpu_supports_indirect_br_lp_instr()) || > + (tval == CFI_TVAL_BCFI_CODE && cpu_supports_shadow_stack())) { > + do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc, > + "Oops - control flow violation"); > + ret = true; > + } > + > + return ret; > +} > + > +/* > + * software check exception is defined with risc-v cfi spec. Software check > + * exception is raised when:- > + * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad` > + * instruction or `label` value programmed in `lpad` instr doesn't > + * match with value setup in `x7`. reported code in `xtval` is 2. > + * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp) > + * and x1/x5. reported code in `xtval` is 3. > + */ > +asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs) > +{ > + if (user_mode(regs)) { > + irqentry_enter_from_user_mode(regs); > + > + /* not a cfi violation, then merge into flow of unknown trap handler */ > + if (!handle_user_cfi_violation(regs)) > + do_trap_unknown(regs); > + > + irqentry_exit_to_user_mode(regs); > + } else { > + /* sw check exception coming from kernel is a bug in kernel */ > + die(regs, "Kernel BUG"); > + } > +} > + > #ifdef CONFIG_MMU > asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) > { >
Hi Clement, Thanks for looking at it. Inline On Thu, Feb 06, 2025 at 02:49:09PM +0100, Clément Léger wrote: > > >On 05/02/2025 02:22, Deepak Gupta wrote: >> zicfiss / zicfilp introduces a new exception to priv isa `software check >> exception` with cause code = 18. This patch implements software check >> exception. > >Hey Deepak, > >While not directly related to this patch, is the exception 18 delegation >documented in the SBI doc ? I mean, should we specify that it is always >delegated when implementing FWFT LANDING_PAD/SHADOW_STACK ? I don't think it's document in SBI spec anywhere. Should it be ? In code, opensbi delegates the exception (SW_CHECK) https://github.com/riscv-software-src/opensbi/commit/110524441a827e026db3547ed03c5723b9c9e211 > >Thanks, > >Clément > >>
On 07/02/2025 22:26, Deepak Gupta wrote: > Hi Clement, > > Thanks for looking at it. Inline > On Thu, Feb 06, 2025 at 02:49:09PM +0100, Clément Léger wrote: >> >> >> On 05/02/2025 02:22, Deepak Gupta wrote: >>> zicfiss / zicfilp introduces a new exception to priv isa `software check >>> exception` with cause code = 18. This patch implements software check >>> exception. >> >> Hey Deepak, >> >> While not directly related to this patch, is the exception 18 delegation >> documented in the SBI doc ? I mean, should we specify that it is always >> delegated when implementing FWFT LANDING_PAD/SHADOW_STACK ? > > I don't think it's document in SBI spec anywhere. Should it be ? That's a good question ! I don't know the process to document that part of the SBI but that would probably be nice to document it anyway I guess. Atish may know what to do with that. Clément > > > In code, opensbi delegates the exception (SW_CHECK) > https://github.com/riscv-software-src/opensbi/ > commit/110524441a827e026db3547ed03c5723b9c9e211 > >> >> Thanks, >> >> Clément >> >>>
diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h index cd627ec289f1..5a27cefd7805 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u); DECLARE_DO_ERROR_INFO(do_trap_ecall_s); DECLARE_DO_ERROR_INFO(do_trap_ecall_m); DECLARE_DO_ERROR_INFO(do_trap_break); +DECLARE_DO_ERROR_INFO(do_trap_software_check); asmlinkage void handle_bad_stack(struct pt_regs *regs); asmlinkage void do_page_fault(struct pt_regs *regs); diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index b28ccc6cdeea..34ed149af5d1 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -40,4 +40,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs) } #endif +bool handle_user_cfi_violation(struct pt_regs *regs); + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 00494b54ff4a..9c00cac3f6f2 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -472,6 +472,9 @@ SYM_DATA_START_LOCAL(excp_vect_table) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ + RISCV_PTR do_trap_unknown /* cause=16 */ + RISCV_PTR do_trap_unknown /* cause=17 */ + RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */ SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) #ifndef CONFIG_MMU diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8ff8e8b36524..3f7709f4595a 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -354,6 +354,49 @@ void do_trap_ecall_u(struct pt_regs *regs) } +#define CFI_TVAL_FCFI_CODE 2 +#define CFI_TVAL_BCFI_CODE 3 +/* handle cfi violations */ +bool handle_user_cfi_violation(struct pt_regs *regs) +{ + bool ret = false; + unsigned long tval = csr_read(CSR_TVAL); + + if ((tval == CFI_TVAL_FCFI_CODE && cpu_supports_indirect_br_lp_instr()) || + (tval == CFI_TVAL_BCFI_CODE && cpu_supports_shadow_stack())) { + do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc, + "Oops - control flow violation"); + ret = true; + } + + return ret; +} + +/* + * software check exception is defined with risc-v cfi spec. Software check + * exception is raised when:- + * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad` + * instruction or `label` value programmed in `lpad` instr doesn't + * match with value setup in `x7`. reported code in `xtval` is 2. + * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp) + * and x1/x5. reported code in `xtval` is 3. + */ +asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + /* not a cfi violation, then merge into flow of unknown trap handler */ + if (!handle_user_cfi_violation(regs)) + do_trap_unknown(regs); + + irqentry_exit_to_user_mode(regs); + } else { + /* sw check exception coming from kernel is a bug in kernel */ + die(regs, "Kernel BUG"); + } +} + #ifdef CONFIG_MMU asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) {
zicfiss / zicfilp introduces a new exception to priv isa `software check exception` with cause code = 18. This patch implements software check exception. Additionally it implements a cfi violation handler which checks for code in xtval. If xtval=2, it means that sw check exception happened because of an indirect branch not landing on 4 byte aligned PC or not landing on `lpad` instruction or label value embedded in `lpad` not matching label value setup in `x7`. If xtval=3, it means that sw check exception happened because of mismatch between link register (x1 or x5) and top of shadow stack (on execution of `sspopchk`). In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was introduced by x86 shadow stack patches. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/entry-common.h | 2 ++ arch/riscv/kernel/entry.S | 3 +++ arch/riscv/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+)