From patchwork Wed Jul 14 14:07:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 112000 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6EE6fJn010560 for ; Wed, 14 Jul 2010 14:06:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756944Ab0GNOGJ (ORCPT ); Wed, 14 Jul 2010 10:06:09 -0400 Received: from perceval.irobotique.be ([92.243.18.41]:52763 "EHLO perceval.irobotique.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756606Ab0GNOGH (ORCPT ); Wed, 14 Jul 2010 10:06:07 -0400 Received: from localhost.localdomain (unknown [91.178.183.65]) by perceval.irobotique.be (Postfix) with ESMTPSA id E4A1635E01; Wed, 14 Jul 2010 14:06:03 +0000 (UTC) From: Laurent Pinchart To: linux-media@vger.kernel.org Cc: sakari.ailus@maxwell.research.nokia.com Subject: [SAMPLE 02/12] v4l: Add 16 bit YUYV and SGRBG10 media bus format codes Date: Wed, 14 Jul 2010 16:07:04 +0200 Message-Id: <1279116434-28278-3-git-send-email-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279114219-27389-1-git-send-email-laurent.pinchart@ideasonboard.com> References: <1279114219-27389-1-git-send-email-laurent.pinchart@ideasonboard.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Jul 2010 14:06:42 +0000 (UTC) diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h index 17219c3..34dd708 100644 --- a/include/linux/v4l2-mediabus.h +++ b/include/linux/v4l2-mediabus.h @@ -43,6 +43,12 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_MBUS_FMT_SGRBG8_1X8, + V4L2_MBUS_FMT_SGRBG10_1X10, + V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8, + V4L2_MBUS_FMT_YUYV16_1X16, + V4L2_MBUS_FMT_UYVY16_1X16, + V4L2_MBUS_FMT_YVYU16_1X16, + V4L2_MBUS_FMT_VYUY16_1X16, }; /**