From patchwork Mon Dec 20 11:37:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 420001 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBKBc77G028629 for ; Mon, 20 Dec 2010 11:38:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757410Ab0LTLhf (ORCPT ); Mon, 20 Dec 2010 06:37:35 -0500 Received: from perceval.ideasonboard.com ([95.142.166.194]:51297 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757401Ab0LTLhd (ORCPT ); Mon, 20 Dec 2010 06:37:33 -0500 Received: from localhost.localdomain (unknown [87.66.44.208]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id DE54035C9A; Mon, 20 Dec 2010 11:37:31 +0000 (UTC) From: Laurent Pinchart To: linux-media@vger.kernel.org Cc: sakari.ailus@maxwell.research.nokia.com Subject: [RFC/PATCH v5 06/13] v4l: Add remaining RAW10 patterns w DPCM pixel code variants Date: Mon, 20 Dec 2010 12:37:18 +0100 Message-Id: <1292845045-7945-7-git-send-email-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1292845045-7945-1-git-send-email-laurent.pinchart@ideasonboard.com> References: <1292845045-7945-1-git-send-email-laurent.pinchart@ideasonboard.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 20 Dec 2010 11:38:09 +0000 (UTC) diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h index b091366..99cfd38 100644 --- a/include/linux/v4l2-mediabus.h +++ b/include/linux/v4l2-mediabus.h @@ -67,16 +67,21 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d, V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e, - /* Bayer - next is 0x300b */ + /* Bayer - next is 0x3010 */ V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001, V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002, + V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b, + V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c, V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009, + V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8 = 0x300d, V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003, V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004, V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005, V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006, V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007, + V4L2_MBUS_FMT_SGBRG10_1X10 = 0x300e, V4L2_MBUS_FMT_SGRBG10_1X10 = 0x300a, + V4L2_MBUS_FMT_SRGGB10_1X10 = 0x300f, V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008, };