@@ -20,6 +20,11 @@ config S5PV310_DEV_PD
help
Compile in platform device definitions for Power Domain
+config S5PV310_DEV_TV
+ bool
+ help
+ Compile in platform device definition for TV interface
+
config S5PV310_SETUP_I2C1
bool
help
@@ -32,6 +32,7 @@ obj-y += dev-audio.o
obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
+obj-$(CONFIG_S5PV310_DEV_TV) += dev-tv.o
obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
@@ -24,6 +24,7 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
@@ -82,6 +83,11 @@ static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
}
+static int s5pv310_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+}
+
static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -132,6 +138,11 @@ static int s5pv310_clk_ip_tv_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
}
+static int s5pv310_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -528,6 +539,31 @@ static struct clk init_clocks_off[] = {
.enable = s5pv310_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
+ .name = "dac",
+ .id = -1,
+ .enable = s5pv310_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "mixer",
+ .id = -1,
+ .enable = s5pv310_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "vp",
+ .id = -1,
+ .enable = s5pv310_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .id = -1,
+ .enable = s5pv310_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "hdmiphy",
+ .id = -1,
+ .enable = s5pv310_clk_hdmiphy_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "hsmmc",
.id = 0,
.parent = &clk_aclk_133.clk,
@@ -805,6 +841,93 @@ static struct clksrc_sources clkset_mout_g2d = {
.nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
};
+/* --------------------------------------
+ * TV subsystem CLOCKS
+ * --------------------------------------
+ */
+
+static struct clk *clkset_sclk_dac_list[] = {
+ [0] = &clk_sclk_vpll.clk,
+ [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+ .sources = clkset_sclk_dac_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+ .clk = {
+ .name = "sclk_dac",
+ .id = -1,
+ .enable = s5pv310_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_sclk_dac,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .id = -1,
+ .parent = &clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_hdmi_list[] = {
+ [0] = &clk_sclk_pixel.clk,
+ [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+ .sources = clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .id = -1,
+ .enable = s5pv310_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_sclk_hdmi,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_mixer_list[] = {
+ [0] = &clk_sclk_dac.clk,
+ [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+ .sources = clkset_sclk_mixer_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk clk_sclk_mixer = {
+ .clk = {
+ .name = "sclk_mixer",
+ .id = -1,
+ .enable = s5pv310_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_sclk_mixer,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+ &clk_sclk_dac,
+ &clk_sclk_pixel,
+ &clk_sclk_hdmi,
+ &clk_sclk_mixer,
+ NULL,
+};
+
+/* -------------------------------------------- */
+
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
@@ -1223,7 +1346,10 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
}
static struct clk *clks[] __initdata = {
- /* Nothing here yet */
+ &clk_sclk_hdmi27m,
+ &clk_sclk_hdmiphy,
+ &clk_sclk_usbphy0,
+ &clk_sclk_usbphy1,
};
void __init s5pv310_register_clocks(void)
@@ -1235,6 +1361,10 @@ void __init s5pv310_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ /* register TV clocks */
+ for (ptr = 0; sclk_tv[ptr]; ++ptr)
+ s3c_register_clksrc(sclk_tv[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
new file mode 100644
@@ -0,0 +1,103 @@
+/* linux/arch/arm/mach-s5pv310/dev-tv.c
+ *
+ * Copyright 20i10 Samsung Electronics
+ * Tomasz Stanislawski <t.stanislaws@samsung.com>
+ *
+ * S5P series device definition for TV device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "plat/tv.h"
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/gfp.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+/* HDMI interface */
+static struct resource s5p_hdmi_resources[] = {
+ [0] = {
+ .start = S5P_PA_HDMI,
+ .end = S5P_PA_HDMI + S5P_SZ_HDMI - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_HDMI,
+ .end = IRQ_HDMI,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s5p_device_hdmi = {
+ .name = "s5p-hdmi",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
+ .resource = s5p_hdmi_resources,
+};
+EXPORT_SYMBOL(s5p_device_hdmi);
+
+/* MIXER */
+static struct resource s5p_mixer_resources[] = {
+ [0] = {
+ .start = S5P_PA_MIXER,
+ .end = S5P_PA_MIXER + S5P_SZ_MIXER - 1,
+ .flags = IORESOURCE_MEM,
+ .name = "mxr"
+ },
+ [1] = {
+ .start = S5P_PA_VP,
+ .end = S5P_PA_VP + S5P_SZ_VP - 1,
+ .flags = IORESOURCE_MEM,
+ .name = "vp"
+ },
+ [2] = {
+ .start = IRQ_MIXER,
+ .end = IRQ_MIXER,
+ .flags = IORESOURCE_IRQ,
+ .name = "irq"
+ },
+};
+
+static struct mxr_platform_data mxr_pdata;
+
+struct platform_device s5p_device_mixer = {
+ .name = "s5p-mixer",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5p_mixer_resources),
+ .resource = s5p_mixer_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &s5p_device_mixer.dev.coherent_dma_mask,
+ .platform_data = &mxr_pdata,
+ }
+};
+EXPORT_SYMBOL(s5p_device_mixer);
+
+static struct mxr_platform_output output[] = {
+ { .output_name = "S5P HDMI connector", .module_name = "s5p-hdmi" },
+};
+
+static struct mxr_platform_data mxr_pdata = {
+ .output = output,
+ .output_cnt = ARRAY_SIZE(output),
+};
+
@@ -121,6 +121,10 @@
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
+/* Set the default NR_IRQS */
+#define IRQ_MIXER COMBINER_IRQ(36, 0)
+#define IRQ_TVENC COMBINER_IRQ(36, 1)
+
#define IRQ_EINT4 COMBINER_IRQ(37, 0)
#define IRQ_EINT5 COMBINER_IRQ(37, 1)
#define IRQ_EINT6 COMBINER_IRQ(37, 2)
@@ -152,4 +152,30 @@
#define S5P_SZ_UART SZ_256
+/* CEC */
+#define S5PV210_PA_CEC (0x100B0000)
+#define S5P_PA_CEC S5PV210_PA_CEC
+#define S5P_SZ_CEC SZ_4K
+
+/* TVOUT */
+#define S5PV210_PA_TVENC (0x12C20000)
+#define S5P_PA_TVENC S5PV210_PA_TVENC
+#define S5P_SZ_TVENC SZ_64K
+
+#define S5PV210_PA_VP (0x12C00000)
+#define S5P_PA_VP S5PV210_PA_VP
+#define S5P_SZ_VP SZ_64K
+
+#define S5PV210_PA_MIXER (0x12C10000)
+#define S5P_PA_MIXER S5PV210_PA_MIXER
+#define S5P_SZ_MIXER SZ_64K
+
+#define S5PV210_PA_HDMI (0x12D00000)
+#define S5P_PA_HDMI S5PV210_PA_HDMI
+#define S5P_SZ_HDMI SZ_1M
+
+#define S5PV210_I2C_HDMI_PHY (0x138E0000)
+#define S5P_I2C_HDMI_PHY S5PV210_I2C_HDMI_PHY
+#define S5P_I2C_HDMI_SZ_PHY SZ_1K
+
#endif /* __ASM_ARCH_MAP_H */
@@ -33,6 +33,7 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -42,6 +43,7 @@
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
@@ -58,6 +60,7 @@
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
@@ -27,4 +27,6 @@
#define S5P_INT_LOCAL_PWR_EN 0x7
+#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
+
#endif /* __ASM_ARCH_REGS_PMU_H */
@@ -135,6 +135,8 @@ extern struct platform_device s5p_device_fimc0;
extern struct platform_device s5p_device_fimc1;
extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_fimc3;
+extern struct platform_device s5p_device_hdmi;
+extern struct platform_device s5p_device_mixer;
extern struct platform_device s5p_device_mfc;
extern struct platform_device s5p_device_mipi_csis0;