From patchwork Wed Apr 6 14:01:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Teresa_G=C3=A1mez?= X-Patchwork-Id: 689881 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p36E6AcG004533 for ; Wed, 6 Apr 2011 14:06:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755986Ab1DFOGI (ORCPT ); Wed, 6 Apr 2011 10:06:08 -0400 Received: from mail.visioncatalog.com ([217.6.246.34]:45626 "EHLO root.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755952Ab1DFOGH convert rfc822-to-8bit (ORCPT ); Wed, 6 Apr 2011 10:06:07 -0400 Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id BDF81BF08A for ; Wed, 6 Apr 2011 16:08:03 +0200 (CEST) Received: from numalfix.phytec.de ([127.0.0.1]) by idefix.phytec.de (Lotus Domino Release 8.5.2 HF194) with ESMTP id 2011040616060523-149887 ; Wed, 6 Apr 2011 16:06:05 +0200 Received: by numalfix.phytec.de (Postfix, from userid 1010) id 3AD8D1A17E5; Wed, 6 Apr 2011 16:02:10 +0200 (CEST) From: =?UTF-8?q?Teresa=20G=C3=A1mez?= To: linux-media@vger.kernel.org Cc: =?UTF-8?q?Teresa=20G=C3=A1mez?= Subject: [PATCH 1/2] mt9v022: fix pixel clock Date: Wed, 6 Apr 2011 16:01:54 +0200 Message-Id: <1302098515-12176-1-git-send-email-t.gamez@phytec.de> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 8.5.2 HF194|November 09, 2010) at 06.04.2011 16:06:05, Serialize by Router on Idefix/Phytec(Release 8.5.2 HF194|November 09, 2010) at 06.04.2011 16:06:05, Serialize complete at 06.04.2011 16:06:05 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 06 Apr 2011 14:06:11 +0000 (UTC) Measurements show that the setup of the pixel clock is not correct. The 'Invert Pixel Clock' bit has to be set to 1 for falling edge and not for rising. Signed-off-by: Teresa Gámez --- drivers/media/video/mt9v022.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c index 6a784c8..dec2a69 100644 --- a/drivers/media/video/mt9v022.c +++ b/drivers/media/video/mt9v022.c @@ -228,7 +228,7 @@ static int mt9v022_set_bus_param(struct soc_camera_device *icd, flags = soc_camera_apply_sensor_flags(icl, flags); - if (flags & SOCAM_PCLK_SAMPLE_RISING) + if (flags & SOCAM_PCLK_SAMPLE_FALLING) pixclk |= 0x10; if (!(flags & SOCAM_HSYNC_ACTIVE_HIGH))