From patchwork Tue Oct 21 11:06:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 5114151 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1ABBC9F374 for ; Tue, 21 Oct 2014 11:07:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21F662012F for ; Tue, 21 Oct 2014 11:07:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 33C6B20123 for ; Tue, 21 Oct 2014 11:07:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755255AbaJULHo (ORCPT ); Tue, 21 Oct 2014 07:07:44 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:59924 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755052AbaJULHn (ORCPT ); Tue, 21 Oct 2014 07:07:43 -0400 Received: by mail-pd0-f178.google.com with SMTP id y10so1151932pdj.9 for ; Tue, 21 Oct 2014 04:07:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=iPM3+hnaY68BhY+5IioOhNXM0fmN13i1ar0hdTFN0SY=; b=YPUpaxdX2ZacsPyoYhVRmHOvoyQ4/snVpJj7Y6J9Lf4K6qacXXigiW96baDUb3+bbR aMaibkmJojrdTpTfwkUK3RnIQO8liVe9Hjs9RGn8dWUZ6YTQc2UY7vj8SYtN+cv7mNSr Opqi8dPZATWHMh9tPleDebeUQBQuAN8F7hzE4F3TQBatsCyJtH7wFEvl+NREDQ5s2KIV Ww7zWM899loAVhHMAJQ6HoU/9IjNrrN6pMmrCh/2zErIc8C/YHBacl25w/zKsYR3efPk L7s0VlwhSr4vFMZ2NBb4PD5pno8bW0ypdw/aWGrmIWEIlH/3Zg/ZWWpjD5XYT3DSykj6 bvMQ== X-Received: by 10.66.242.14 with SMTP id wm14mr33870086pac.77.1413889663100; Tue, 21 Oct 2014 04:07:43 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id s9sm11680849pdp.1.2014.10.21.04.07.38 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 04:07:42 -0700 (PDT) From: Arun Kumar K To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: k.debski@samsung.com, wuchengli@chromium.org, posciak@chromium.org, arun.m@samsung.com, ihf@chromium.org, prathyush.k@samsung.com, kiran@chromium.org, arunkk.samsung@gmail.com Subject: [PATCH v3 05/13] [media] s5p-mfc: keep RISC ON during reset for V7/V8 Date: Tue, 21 Oct 2014 16:36:59 +0530 Message-Id: <1413889627-8431-6-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1413889627-8431-1-git-send-email-arun.kk@samsung.com> References: <1413889627-8431-1-git-send-email-arun.kk@samsung.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kiran AVND Reset sequence for MFC V7 and V8 do not need RISC_ON to be set to 0, while for MFC V6 it is still needed. Also, remove a couple of register settings during Reset which are not needed from V6 onwards. Signed-off-by: Kiran AVND Signed-off-by: Arun Kumar K --- drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 1 + drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c | 25 ++++++++++++++--------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index 3e41ca1..5b0c334 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -340,6 +340,7 @@ struct s5p_mfc_dev { struct s5p_mfc_hw_cmds *mfc_cmds; const struct s5p_mfc_regs *mfc_regs; enum s5p_mfc_fw_ver fw_ver; + bool risc_on; /* indicates if RISC is on or off */ }; /** diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index 0c885a8..f5bb6b2 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -139,12 +139,6 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) mfc_debug_enter(); if (IS_MFCV6_PLUS(dev)) { - /* Reset IP */ - /* except RISC, reset */ - mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6); - /* reset release */ - mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6); - /* Zero Initialization of MFC registers */ mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6); mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6); @@ -153,8 +147,13 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++) mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4)); - /* Reset */ - mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6); + /* Reset + * set RISC_ON to 0 during power_on & wake_up. + * V6 needs RISC_ON set to 0 during reset also. + */ + if ((!dev->risc_on) || (!IS_MFCV7(dev))) + mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6); + mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6); mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6); } else { @@ -226,6 +225,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) /* 0. MFC reset */ mfc_debug(2, "MFC reset..\n"); s5p_mfc_clock_on(); + dev->risc_on = 0; ret = s5p_mfc_reset(dev); if (ret) { mfc_err("Failed to reset MFC - timeout\n"); @@ -238,8 +238,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) s5p_mfc_clear_cmds(dev); /* 3. Release reset signal to the RISC */ s5p_mfc_clean_dev_int_flags(dev); - if (IS_MFCV6_PLUS(dev)) + if (IS_MFCV6_PLUS(dev)) { + dev->risc_on = 1; mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6); + } else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); @@ -336,6 +338,7 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) /* 0. MFC reset */ mfc_debug(2, "MFC reset..\n"); s5p_mfc_clock_on(); + dev->risc_on = 0; ret = s5p_mfc_reset(dev); if (ret) { mfc_err("Failed to reset MFC - timeout\n"); @@ -354,8 +357,10 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) return ret; } /* 4. Release reset signal to the RISC */ - if (IS_MFCV6_PLUS(dev)) + if (IS_MFCV6_PLUS(dev)) { + dev->risc_on = 1; mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6); + } else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); mfc_debug(2, "Ok, now will write a command to wakeup the system\n");