From patchwork Wed Apr 13 12:01:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "tiffany.lin" X-Patchwork-Id: 8821711 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7AC369F39A for ; Wed, 13 Apr 2016 12:03:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D595A20373 for ; Wed, 13 Apr 2016 12:02:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4075720375 for ; Wed, 13 Apr 2016 12:02:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031095AbcDMMCp (ORCPT ); Wed, 13 Apr 2016 08:02:45 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:38015 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1031049AbcDMMCK (ORCPT ); Wed, 13 Apr 2016 08:02:10 -0400 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 624710394; Wed, 13 Apr 2016 20:01:59 +0800 Received: from localhost.localdomain (10.21.14.115) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Wed, 13 Apr 2016 20:01:58 +0800 From: Tiffany Lin To: Hans Verkuil , , Rob Herring , Mauro Carvalho Chehab , Matthias Brugger , Daniel Kurtz , Pawel Osciak CC: Eddie Huang , Yingjoe Chen , , , , , , , , Tiffany Lin Subject: [PATCH 7/7] arm64: dts: mediatek: Add Video Encoder for MT8173 Date: Wed, 13 Apr 2016 20:01:55 +0800 Message-ID: <1460548915-17536-8-git-send-email-tiffany.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1460548915-17536-7-git-send-email-tiffany.lin@mediatek.com> References: <1460548915-17536-1-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-2-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-3-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-4-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-5-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-6-git-send-email-tiffany.lin@mediatek.com> <1460548915-17536-7-git-send-email-tiffany.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add video decoder node for MT8173 Signed-off-by: Tiffany Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 26aeffe..32b555e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1124,6 +1124,44 @@ #clock-cells = <1>; }; + vcodec_dec: vcodec@16000000 { + compatible = "mediatek,mt8173-vcodec-dec"; + reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ + <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_LD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_CM */ + <0 0x16023000 0 0x1000>, /* VDEC_AD */ + <0 0x16024000 0 0x1000>, /* VDEC_AV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VDEC_HWD */ + <0 0x16027000 0 0x800>, /* VDEC_HWQ */ + <0 0x16027800 0 0x800>, /* VDEC_HWB */ + <0 0x16028400 0 0x400>; /* VDEC_HWG */ + interrupts = ; + mediatek,larb = <&larb1>; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; + mediatek,vpu = <&vpu>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_VCODECPLL>; + clock-names = "vcodecpll", + "univpll_d2", + "clk_cci400_sel", + "vdec_sel", + "vdecpll"; + }; + larb1: larb@16010000 { compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x16010000 0 0x1000>;