From patchwork Mon Jun 26 18:12:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 9810207 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4078C60209 for ; Mon, 26 Jun 2017 18:12:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FA3128520 for ; Mon, 26 Jun 2017 18:12:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 344DB285E8; Mon, 26 Jun 2017 18:12:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3C71285DA for ; Mon, 26 Jun 2017 18:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751813AbdFZSMr (ORCPT ); Mon, 26 Jun 2017 14:12:47 -0400 Received: from galahad.ideasonboard.com ([185.26.127.97]:56948 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbdFZSMo (ORCPT ); Mon, 26 Jun 2017 14:12:44 -0400 Received: from avalon.bb.dnainternet.fi (dfj612ybrt5fhg77mgycy-3.rev.dnainternet.fi [IPv6:2001:14ba:21f5:5b00:2e86:4862:ef6a:2804]) by galahad.ideasonboard.com (Postfix) with ESMTPSA id 141A621438; Mon, 26 Jun 2017 20:12:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1498500746; bh=DRd2kpsd5W05je0qOKU65YMe6uEiRkAMBOO6gmcU6KE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M/YcgXEBtaXGtxc7DG97vwxW5aOPvsRfZxUIyXojE/VXALKeWLoA3chk0luCEf2RW X31CF3jMyDCzGOqlr6oEHxNQEKg0GmXvPVfGJK17oGgSdsqCfA5jlOdgbom9/kczh/ 2tYvezkg8rcC4wMiUue7wyyPZ8Yp13YtbsxZiBvs= From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 13/14] drm: rcar-du: Restrict DPLL duty cycle workaround to H3 ES1.x Date: Mon, 26 Jun 2017 21:12:25 +0300 Message-Id: <20170626181226.29575-14-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> References: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The H3 ES1.x exhibits dot clock duty cycle stability issues. We can work around them by configuring the DPLL to twice the desired frequency, coupled with a /2 post-divider. This isn't needed on other SoCs and breaks HDMI output on M3-W for a currently unknown reason, so restrict the workaround to H3 ES1.x. From an implementation point of view, move work around handling outside of the rcar_du_dpll_divider() function by requesting a x2 DPLL output frequency explicitly. The existing post-divider calculation mechanism will then take care of dividing the clock by two automatically. While at it, print a more useful debugging message to ease debugging clock rate issues. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 37 +++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 8f942ebdd0c6..6c29981377c0 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -129,10 +130,8 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc, for (fdpll = 1; fdpll < 32; fdpll++) { unsigned long output; - /* 1/2 (FRQSEL=1) for duty rate 50% */ output = input * (n + 1) / (m + 1) - / (fdpll + 1) / 2; - + / (fdpll + 1); if (output >= 400000000) continue; @@ -158,6 +157,11 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc, best_diff); } +static const struct soc_device_attribute rcar_du_r8a7795_es1[] = { + { .soc_id = "r8a7795", .revision = "ES1.*" }, + { /* sentinel */ } +}; + static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) { const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; @@ -185,7 +189,20 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) extclk = clk_get_rate(rcrtc->extclock); if (rcdu->info->dpll_ch & (1 << rcrtc->index)) { - rcar_du_dpll_divider(rcrtc, &dpll, extclk, mode_clock); + unsigned long target = mode_clock; + + /* + * The H3 ES1.x exhibits dot clock duty cycle stability + * issues. We can work around them by configuring the + * DPLL to twice the desired frequency, coupled with a + * /2 post-divider. This isn't needed on other SoCs and + * breaks HDMI output on M3-W for a currently unknown + * reason, so restrict the workaround to H3 ES1.x. + */ + if (soc_device_match(rcar_du_r8a7795_es1)) + target *= 2; + + rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); extclk = dpll.output; } @@ -197,8 +214,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) if (abs((long)extrate - (long)mode_clock) < abs((long)rate - (long)mode_clock)) { - dev_dbg(rcrtc->group->dev->dev, - "crtc%u: using external clock\n", rcrtc->index); if (rcdu->info->dpll_ch & (1 << rcrtc->index)) { u32 dpllcr = DPLLCR_CODE | DPLLCR_CLKE @@ -215,12 +230,14 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); - - escr = ESCR_DCLKSEL_DCLKIN | 1; - } else { - escr = ESCR_DCLKSEL_DCLKIN | extdiv; } + + escr = ESCR_DCLKSEL_DCLKIN | extdiv; } + + dev_dbg(rcrtc->group->dev->dev, + "mode clock %lu extrate %lu rate %lu ESCR 0x%08x\n", + mode_clock, extrate, rate, escr); } rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,