Message ID | 20180710080114.31469-12-paul.kocialkowski@bootlin.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Tue, Jul 10, 2018 at 4:01 PM, Paul Kocialkowski <paul.kocialkowski@bootlin.com> wrote: > From: Maxime Ripard <maxime.ripard@bootlin.com> > > This adds support for the C1 SRAM region (to be used with the SRAM > controller driver) for sun5i-based platforms. The region is shared > between the Video Engine and the CPU. > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> But again, see discussion about SRAM compatibles.
On Tue, Jul 10, 2018 at 10:56:23PM +0800, Chen-Yu Tsai wrote: > On Tue, Jul 10, 2018 at 4:01 PM, Paul Kocialkowski > <paul.kocialkowski@bootlin.com> wrote: > > From: Maxime Ripard <maxime.ripard@bootlin.com> > > > > This adds support for the C1 SRAM region (to be used with the SRAM > > controller driver) for sun5i-based platforms. The region is shared > > between the Video Engine and the CPU. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > But again, see discussion about SRAM compatibles. I've fixed the SRAM C size (which is 0xd0000 and not 0x80000) and applied, thanks! Maxime
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 68711954c293..51dcefc76c12 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -137,6 +137,20 @@ status = "disabled"; }; + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun5i-a13-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>;