From patchwork Sun May 5 14:00:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lubomir Rintel X-Patchwork-Id: 10930167 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 24B43933 for ; Sun, 5 May 2019 14:02:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13CCE285E0 for ; Sun, 5 May 2019 14:02:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 08198285E5; Sun, 5 May 2019 14:02:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4015285E0 for ; Sun, 5 May 2019 14:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727899AbfEEOBC (ORCPT ); Sun, 5 May 2019 10:01:02 -0400 Received: from shell.v3.sk ([90.176.6.54]:55699 "EHLO shell.v3.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726397AbfEEOBB (ORCPT ); Sun, 5 May 2019 10:01:01 -0400 Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id 52347103D2F; Sun, 5 May 2019 16:00:57 +0200 (CEST) Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id Yhr0dDZ7rP2U; Sun, 5 May 2019 16:00:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id BDCAD103D25; Sun, 5 May 2019 16:00:40 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.v3.sk Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id rR14XGBvRG76; Sun, 5 May 2019 16:00:37 +0200 (CEST) Received: from nedofet.lan (ip-89-102-31-34.net.upcbroadband.cz [89.102.31.34]) by zimbra.v3.sk (Postfix) with ESMTPSA id 78DA5103D29; Sun, 5 May 2019 16:00:36 +0200 (CEST) From: Lubomir Rintel To: Mauro Carvalho Chehab , Jonathan Corbet , linux-media@vger.kernel.org Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, James Cameron , Pavel Machek , Libin Yang , Albert Wang , jacopo mondi , Sakari Ailus , Lubomir Rintel Subject: [PATCH v5 03/10] [media] marvell-ccic: don't generate EOF on parallel bus Date: Sun, 5 May 2019 16:00:24 +0200 Message-Id: <20190505140031.9636-4-lkundrak@v3.sk> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505140031.9636-1-lkundrak@v3.sk> References: <20190505140031.9636-1-lkundrak@v3.sk> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The commit 05fed81625bf ("[media] marvell-ccic: add MIPI support for marvell-ccic driver") that claimed to add CSI2 turned on C0_EOF_VSYNC for parallel bus without a very good explanation. That broke camera on OLPC XO-1.75 which precisely uses a sensor on a parallel bus. Revert that chunk. Tested on an OLPC XO-1.75. Fixes: 05fed81625bf755cc67c5864cdfd18b69ea828d1 Signed-off-by: Lubomir Rintel --- drivers/media/platform/marvell-ccic/mcam-core.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/media/platform/marvell-ccic/mcam-core.c b/drivers/media/platform/marvell-ccic/mcam-core.c index d97f39bde9bd6..d24e5b7a3bc52 100644 --- a/drivers/media/platform/marvell-ccic/mcam-core.c +++ b/drivers/media/platform/marvell-ccic/mcam-core.c @@ -792,12 +792,6 @@ static void mcam_ctlr_image(struct mcam_camera *cam) * Make sure it knows we want to use hsync/vsync. */ mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK); - /* - * This field controls the generation of EOF(DVP only) - */ - if (cam->bus_type != V4L2_MBUS_CSI2_DPHY) - mcam_reg_set_bit(cam, REG_CTRL0, - C0_EOF_VSYNC | C0_VEDGE_CTRL); }